xref: /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala (revision c6d439803a044ea209139672b25e35fe8d7f4aa0) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3*
4* XiangShan is licensed under Mulan PSL v2.
5* You can use this software according to the terms and conditions of the Mulan PSL v2.
6* You may obtain a copy of Mulan PSL v2 at:
7*          http://license.coscl.org.cn/MulanPSL2
8*
9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
12*
13* See the Mulan PSL v2 for more details.
14***************************************************************************************/
15
16package xiangshan.backend.rename
17
18import chipsalliance.rocketchip.config.Parameters
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23
24class BusyTableReadIO(implicit p: Parameters) extends XSBundle {
25  val req = Input(UInt(PhyRegIdxWidth.W))
26  val resp = Output(Bool())
27}
28
29class BusyTable(numReadPorts: Int, numWritePorts: Int)(implicit p: Parameters) extends XSModule {
30  val io = IO(new Bundle() {
31    val flush = Input(Bool())
32    // set preg state to busy
33    val allocPregs = Vec(RenameWidth, Flipped(ValidIO(UInt(PhyRegIdxWidth.W))))
34    // set preg state to ready (write back regfile + roq walk)
35    val wbPregs = Vec(numWritePorts, Flipped(ValidIO(UInt(PhyRegIdxWidth.W))))
36    // read preg state
37    val read = Vec(numReadPorts, new BusyTableReadIO)
38  })
39
40  val table = RegInit(0.U(NRPhyRegs.W))
41
42  def reqVecToMask(rVec: Vec[Valid[UInt]]): UInt = {
43    ParallelOR(rVec.map(v => Mux(v.valid, UIntToOH(v.bits), 0.U)))
44  }
45
46  val wbMask = reqVecToMask(io.wbPregs)
47  val allocMask = reqVecToMask(io.allocPregs)
48
49  val tableAfterWb = table & (~wbMask).asUInt
50  val tableAfterAlloc = tableAfterWb | allocMask
51
52  io.read.map(r => r.resp := !table(r.req))
53
54  table := tableAfterAlloc
55
56  when(io.flush){
57    table := 0.U(NRPhyRegs.W)
58  }
59
60  XSDebug(p"table    : ${Binary(table)}\n")
61  XSDebug(p"tableNext: ${Binary(tableAfterAlloc)}\n")
62  XSDebug(p"allocMask: ${Binary(allocMask)}\n")
63  XSDebug(p"wbMask   : ${Binary(wbMask)}\n")
64  for (i <- 0 until NRPhyRegs) {
65    XSDebug(table(i), "%d is busy\n", i.U)
66  }
67
68  XSPerfAccumulate("busy_count", PopCount(table))
69}
70