1152b56fdSAllen// See LICENSE.SiFive for license details. 2152b56fdSAllen 3152b56fdSAllenpackage xiangshan.cache 4152b56fdSAllen 5152b56fdSAllenimport chisel3._ 6152b56fdSAllenimport chisel3.util._ 7222e17e5Slinjiaweiimport xiangshan.{HasXSParameter, XSBundle, XSModule} 8152b56fdSAllen 9152b56fdSAllen// this file contains common building blocks that can be shared by ICache and DCache 10152b56fdSAllen// this is the common parameter base for L1 ICache and L1 DCache 11152b56fdSAllentrait L1CacheParameters { 12152b56fdSAllen def nSets: Int 13152b56fdSAllen def nWays: Int 14152b56fdSAllen def rowBits: Int 15152b56fdSAllen def blockBytes: Int 16152b56fdSAllen} 17152b56fdSAllen 18152b56fdSAllentrait HasL1CacheParameters extends HasXSParameter 19152b56fdSAllen with MemoryOpConstants { 20152b56fdSAllen val cacheParams: L1CacheParameters 21152b56fdSAllen 22152b56fdSAllen def nSets = cacheParams.nSets 234948f48aSAllen def nWays = cacheParams.nWays 244948f48aSAllen def blockBytes = cacheParams.blockBytes 25*b3fc7151SAllen def blockBits = blockBytes * 8 264948f48aSAllen 27152b56fdSAllen def idxBits = log2Up(cacheParams.nSets) 284948f48aSAllen def wayBits = log2Up(nWays) 294948f48aSAllen def blockOffBits = log2Up(cacheParams.blockBytes) 304948f48aSAllen 31152b56fdSAllen def untagBits = blockOffBits + idxBits 32152b56fdSAllen // 4K page 33152b56fdSAllen def pgIdxBits = 12 34152b56fdSAllen def pgUntagBits = untagBits min pgIdxBits 35152b56fdSAllen def tagBits = PAddrBits - pgUntagBits 364948f48aSAllen 374948f48aSAllen // the basic unit at which we store contents 384948f48aSAllen // SRAM bank width 39152b56fdSAllen def rowBits = cacheParams.rowBits 40152b56fdSAllen def rowBytes = rowBits/8 41152b56fdSAllen def rowOffBits = log2Up(rowBytes) 424948f48aSAllen // the number of rows in a block 434948f48aSAllen def blockRows = blockBytes / rowBytes 44152b56fdSAllen 454948f48aSAllen // outer bus width 464948f48aSAllen def beatBits = l1BusDataWidth 474948f48aSAllen def beatBytes = beatBits / 8 484948f48aSAllen def refillCycles = blockBytes / beatBytes 494948f48aSAllen def beatOffBits = log2Up(beatBytes) 504948f48aSAllen 514948f48aSAllen // inner bus width(determined by XLEN) 524948f48aSAllen def wordBits = DataBits 534948f48aSAllen def wordBytes = wordBits / 8 544948f48aSAllen def wordOffBits = log2Up(wordBytes) 554948f48aSAllen // the number of words in a block 564948f48aSAllen def blockWords = blockBytes / wordBytes 574948f48aSAllen 584948f48aSAllen def idxMSB = untagBits-1 594948f48aSAllen def idxLSB = blockOffBits 604948f48aSAllen def offsetmsb = idxLSB-1 614948f48aSAllen def offsetlsb = wordOffBits 624948f48aSAllen 634948f48aSAllen def get_tag(addr: UInt) = (addr >> untagBits).asUInt() 644948f48aSAllen def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) 654948f48aSAllen def get_block(addr: UInt) = addr >> blockOffBits 664948f48aSAllen def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits 674948f48aSAllen 684948f48aSAllen def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits) 694948f48aSAllen def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits) 704948f48aSAllen def get_word(addr: UInt) = addr(blockOffBits - 1, wordOffBits) 714948f48aSAllen 724948f48aSAllen def beatRows = beatBits/rowBits 734948f48aSAllen def rowWords = rowBits/wordBits 744948f48aSAllen 754948f48aSAllen def full_divide(a: Int, b: Int) = a >= b && isPow2(a / b) 76152b56fdSAllen} 77152b56fdSAllen 78152b56fdSAllenabstract class L1CacheModule extends XSModule 79152b56fdSAllen with HasL1CacheParameters 80152b56fdSAllen 81152b56fdSAllenabstract class L1CacheBundle extends XSBundle 82152b56fdSAllen with HasL1CacheParameters 83