11f0e2dc7SJiawei Lin/*************************************************************************************** 21f0e2dc7SJiawei Lin* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 31f0e2dc7SJiawei Lin* Copyright (c) 2020-2021 Peng Cheng Laboratory 41f0e2dc7SJiawei Lin* 51f0e2dc7SJiawei Lin* XiangShan is licensed under Mulan PSL v2. 61f0e2dc7SJiawei Lin* You can use this software according to the terms and conditions of the Mulan PSL v2. 71f0e2dc7SJiawei Lin* You may obtain a copy of Mulan PSL v2 at: 81f0e2dc7SJiawei Lin* http://license.coscl.org.cn/MulanPSL2 91f0e2dc7SJiawei Lin* 101f0e2dc7SJiawei Lin* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 111f0e2dc7SJiawei Lin* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 121f0e2dc7SJiawei Lin* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 131f0e2dc7SJiawei Lin* 141f0e2dc7SJiawei Lin* See the Mulan PSL v2 for more details. 151f0e2dc7SJiawei Lin***************************************************************************************/ 161f0e2dc7SJiawei Lin 171f0e2dc7SJiawei Linpackage xiangshan.cache 181f0e2dc7SJiawei Lin 191f0e2dc7SJiawei Linimport chisel3._ 20*4ccb2e8bSYanqin Liimport chisel3.util.RegEnable 21fc00d282SYinan Xuimport difftest.common.DifftestMem 22fc00d282SYinan Xuimport org.chipsalliance.cde.config.Parameters 231f0e2dc7SJiawei Linimport xiangshan._ 241f0e2dc7SJiawei Lin 251f0e2dc7SJiawei Linclass FakeDCache()(implicit p: Parameters) extends XSModule with HasDCacheParameters { 261f0e2dc7SJiawei Lin val io = IO(new DCacheIO) 271f0e2dc7SJiawei Lin 281f0e2dc7SJiawei Lin io := DontCare 291f0e2dc7SJiawei Lin // to LoadUnit 301f0e2dc7SJiawei Lin for (i <- 0 until LoadPipelineWidth) { 31fc00d282SYinan Xu val ram = DifftestMem(64L * 1024 * 1024 * 1024, 8) 32fc00d282SYinan Xu val ren = RegNext(io.lsu.load(i).req.valid) 33fc00d282SYinan Xu val raddr = ((io.lsu.load(i).s1_paddr_dup_dcache - "h80000000".U) >> 3).asUInt 341f0e2dc7SJiawei Lin 351f0e2dc7SJiawei Lin io.lsu.load(i).req.ready := true.B 36fc00d282SYinan Xu io.lsu.load(i).resp.valid := RegNext(ren && !io.lsu.load(i).s1_kill) 37fc00d282SYinan Xu io.lsu.load(i).resp.bits.data := ram.readAndHold(raddr, ren) 381f0e2dc7SJiawei Lin io.lsu.load(i).resp.bits.miss := false.B 391f0e2dc7SJiawei Lin io.lsu.load(i).resp.bits.replay := false.B 401f0e2dc7SJiawei Lin io.lsu.load(i).resp.bits.id := DontCare 4103efd994Shappy-lx io.lsu.load(i).s2_hit := true.B 421f0e2dc7SJiawei Lin io.lsu.load(i).s1_disable_fast_wakeup := false.B 431f0e2dc7SJiawei Lin } 441f0e2dc7SJiawei Lin // to LSQ 45692e2fafSHuijin Li //io.lsu.lsq.valid := false.B 46692e2fafSHuijin Li //io.lsu.lsq.bits := DontCare 471f0e2dc7SJiawei Lin // to Store Buffer 481f0e2dc7SJiawei Lin io.lsu.store.req.ready := true.B 49ad3ba452Szhanglinjuan io.lsu.store.main_pipe_hit_resp := DontCare 50ffd3154dSCharlieLiu //io.lsu.store.refill_hit_resp := DontCare 51ad3ba452Szhanglinjuan io.lsu.store.replay_resp := DontCare 52ad3ba452Szhanglinjuan io.lsu.store.main_pipe_hit_resp.valid := RegNext(io.lsu.store.req.valid) 53*4ccb2e8bSYanqin Li io.lsu.store.main_pipe_hit_resp.bits.id := RegEnable(io.lsu.store.req.bits.id, io.lsu.store.req.valid) 541f0e2dc7SJiawei Lin // to atomics 551f0e2dc7SJiawei Lin val amoHelper = Module(new AMOHelper) 561f0e2dc7SJiawei Lin amoHelper.clock := clock 571f0e2dc7SJiawei Lin amoHelper.enable := io.lsu.atomics.req.valid && !reset.asBool 581f0e2dc7SJiawei Lin amoHelper.cmd := io.lsu.atomics.req.bits.cmd 591f0e2dc7SJiawei Lin amoHelper.addr := io.lsu.atomics.req.bits.addr 6062cb71fbShappy-lx amoHelper.wdata := io.lsu.atomics.req.bits.amo_data 6162cb71fbShappy-lx amoHelper.mask := io.lsu.atomics.req.bits.amo_mask 621f0e2dc7SJiawei Lin io.lsu.atomics.req.ready := true.B 631f0e2dc7SJiawei Lin io.lsu.atomics.resp.valid := RegNext(io.lsu.atomics.req.valid) 6462cb71fbShappy-lx // assert(!io.lsu.atomics.resp.valid || io.lsu.atomics.resp.ready) 651f0e2dc7SJiawei Lin io.lsu.atomics.resp.bits.data := amoHelper.rdata 661f0e2dc7SJiawei Lin io.lsu.atomics.resp.bits.replay := false.B 671f0e2dc7SJiawei Lin io.lsu.atomics.resp.bits.id := 1.U 681f0e2dc7SJiawei Lin}