xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision a0d436a92dcaf9d4b935f821a9cc70e100573d1a) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils.XSDebug
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8import xiangshan.cache._
9
10trait HasPdconst{ this: XSModule =>
11  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
12  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
13  def brInfo(instr: UInt) = {
14    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
15    val rd = Mux(isRVC(instr), instr(12), instr(11,7))
16    val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15))
17    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd)
18    val isRet = brType === BrType.jalr && isLink(rs) && !isCall
19    List(brType, isCall, isRet)
20  }
21}
22
23object BrType {
24  def notBr   = "b00".U
25  def branch  = "b01".U
26  def jal     = "b10".U
27  def jalr    = "b11".U
28  def apply() = UInt(2.W)
29}
30
31object ExcType {  //TODO:add exctype
32  def notExc = "b000".U
33  def apply() = UInt(3.W)
34}
35
36class PreDecodeInfo extends XSBundle {  // 8 bit
37  val isRVC   = Bool()
38  val brType  = UInt(2.W)
39  val isCall  = Bool()
40  val isRet   = Bool()
41  val excType = UInt(3.W)
42  def isBr = brType === BrType.branch
43  def isJal = brType === BrType.jal
44  def isJalr = brType === BrType.jalr
45  def notCFI = brType === BrType.notBr
46}
47
48class PreDecodeResp extends XSBundle {
49  val instrs = Vec(PredictWidth, UInt(32.W))
50  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
51  val mask = UInt(PredictWidth.W)
52  val pd = Vec(PredictWidth, (new PreDecodeInfo))
53}
54
55class PreDecode extends XSModule with HasPdconst{
56  val io = IO(new Bundle() {
57    val in = Input(new ICacheResp)
58    val prev = Flipped(ValidIO(UInt(16.W)))
59    val out = Output(new PreDecodeResp)
60  })
61
62  val data = io.in.data
63  val mask = io.in.mask
64
65  val insts = Wire(Vec(PredictWidth, UInt(32.W)))
66  val instsMask = Wire(Vec(PredictWidth, Bool()))
67  val instsRVC = Wire(Vec(PredictWidth,Bool()))
68  val instsPC = Wire(Vec(PredictWidth, UInt(VAddrBits.W)))
69  // val nextHalf = Wire(UInt(16.W))
70
71  val lastHalfInstrIdx = PopCount(mask) - 1.U
72
73  for (i <- 0 until PredictWidth) {
74    val inst = Wire(UInt(32.W))
75    val valid = Wire(Bool())
76    val pc = io.in.pc + (i << 1).U - Mux(io.prev.valid && (i.U === 0.U), 2.U, 0.U)
77
78    if (i==0) {
79      inst := Mux(io.prev.valid, Cat(data(15,0), io.prev.bits), data(31,0))
80      // valid := Mux(lastHalfInstrIdx === 0.U, isRVC(inst), true.B)
81      valid := Mux(lastHalfInstrIdx === 0.U, Mux(!io.prev.valid, isRVC(inst), true.B), true.B)
82    } else if (i==1) {
83      inst := data(47,16)
84      valid := (io.prev.valid || !(instsMask(0) && !isRVC(insts(0)))) && Mux(lastHalfInstrIdx === 1.U, isRVC(inst), true.B)
85    } else if (i==PredictWidth-1) {
86      inst := Cat(0.U(16.W), data(i*16+15, i*16))
87      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
88    } else {
89      inst := data(i*16+31, i*16)
90      valid := !(instsMask(i-1) && !isRVC(insts(i-1))) && Mux(i.U === lastHalfInstrIdx, isRVC(inst), true.B)
91    }
92
93    insts(i) := inst
94    instsRVC(i) := isRVC(inst)
95    instsMask(i) := mask(i) && valid
96    instsPC(i) := pc
97
98    val brType::isCall::isRet::Nil = brInfo(inst)
99    io.out.pd(i).isRVC := instsRVC(i)
100    io.out.pd(i).brType := brType
101    io.out.pd(i).isCall := isCall
102    io.out.pd(i).isRet := isRet
103    io.out.pd(i).excType := ExcType.notExc
104    io.out.instrs(i) := insts(i)
105    io.out.pc(i) := instsPC(i)
106
107  }
108  io.out.mask := instsMask.asUInt
109
110  for (i <- 0 until PredictWidth) {
111    XSDebug(true.B,
112      p"instr ${Hexadecimal(io.out.instrs(i))}, " +
113      p"mask ${Binary(instsMask(i))}, " +
114      p"pc ${Hexadecimal(io.out.pc(i))}, " +
115      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
116      p"brType ${Binary(io.out.pd(i).brType)}, " +
117      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
118      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
119    )
120  }
121}
122