xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision d9469c00c0ff92207955dcdff2c9085ea391c88f) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils._
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8import xiangshan.cache._
9
10trait HasPdconst{ this: XSModule =>
11  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
12  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
13  def brInfo(instr: UInt) = {
14    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
15    val rd = Mux(isRVC(instr), instr(12), instr(11,7))
16    val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15))
17    val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64
18    val isRet = brType === BrType.jalr && isLink(rs) && !isCall
19    List(brType, isCall, isRet)
20  }
21}
22
23object BrType {
24  def notBr   = "b00".U
25  def branch  = "b01".U
26  def jal     = "b10".U
27  def jalr    = "b11".U
28  def apply() = UInt(2.W)
29}
30
31object ExcType {  //TODO:add exctype
32  def notExc = "b000".U
33  def apply() = UInt(3.W)
34}
35
36class PreDecodeInfo extends XSBundle {  // 8 bit
37  val isRVC   = Bool()
38  val brType  = UInt(2.W)
39  val isCall  = Bool()
40  val isRet   = Bool()
41  val excType = UInt(3.W)
42  def isBr = brType === BrType.branch
43  def isJal = brType === BrType.jal
44  def isJalr = brType === BrType.jalr
45  def notCFI = brType === BrType.notBr
46}
47
48class PreDecodeResp extends XSBundle with HasIFUConst {
49  val instrs = Vec(PredictWidth, UInt(32.W))
50  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
51  val mask = UInt(PredictWidth.W)
52  // one for the first bank
53  val lastHalf = UInt(nBanksInPacket.W)
54  val pd = Vec(PredictWidth, (new PreDecodeInfo))
55}
56
57class PreDecode extends XSModule with HasPdconst with HasIFUConst {
58  val io = IO(new Bundle() {
59    val in = Input(new ICacheResp)
60    val prev = Flipped(ValidIO(UInt(16.W)))
61    val out = Output(new PreDecodeResp)
62  })
63
64  val data = io.in.data
65  val mask = io.in.mask
66
67  val validCount = PopCount(mask)
68  val bankAlignedPC = bankAligned(io.in.pc)
69  val bankOffset = offsetInBank(io.in.pc)
70  val isAligned = bankOffset === 0.U
71
72  val firstValidIdx = bankOffset // io.prev.valid should only occur with firstValidIdx = 0
73  XSError(firstValidIdx =/= 0.U && io.prev.valid, p"pc:${io.in.pc}, mask:${io.in.mask}, prevhalfInst valid occurs on unaligned fetch packet\n")
74  // val lastHalfInstrIdx = Mux(isInLastBank(pc), (bankWidth-1).U, (bankWidth*2-1).U)
75  // in case loop buffer gives a packet ending at an unaligned position
76  val lastHalfInstrIdx = PriorityMux(Reverse(mask), (PredictWidth-1 to 0 by -1).map(i => i.U))
77
78  val insts = Wire(Vec(PredictWidth, UInt(32.W)))
79  val instsMask = Wire(Vec(PredictWidth, Bool()))
80  val instsEndMask = Wire(Vec(PredictWidth, Bool()))
81  val instsRVC = Wire(Vec(PredictWidth,Bool()))
82  val instsPC = Wire(Vec(PredictWidth, UInt(VAddrBits.W)))
83
84  val rawInsts = VecInit((0 until PredictWidth).map(i => if (i == PredictWidth-1) Cat(0.U(16.W), data(i*16+15, i*16))
85                                                         else data(i*16+31, i*16)))
86  // val nextHalf = Wire(UInt(16.W))
87
88  val lastHalf = Wire(Vec(nBanksInPacket, UInt(1.W)))
89
90  for (i <- 0 until PredictWidth) {
91    val inst = WireInit(rawInsts(i))
92    val validStart = Wire(Bool()) // is the beginning of a valid inst
93    val validEnd = Wire(Bool())  // is the end of a valid inst
94    val pc = bankAlignedPC + (i << 1).U - Mux(io.prev.valid && (i.U === firstValidIdx), 2.U, 0.U)
95
96    val isFirstInPacket = i.U === firstValidIdx
97    val isLastInPacket = i.U === lastHalfInstrIdx
98    val currentRVC = isRVC(insts(i))
99
100    val lastIsValidEnd = if (i == 0) { !io.prev.valid } else { instsEndMask(i-1) || isFirstInPacket }
101
102    inst := Mux(io.prev.valid && i.U === 0.U, Cat(rawInsts(i)(15,0), io.prev.bits), rawInsts(i))
103
104    validStart := lastIsValidEnd && !(isLastInPacket && !currentRVC)
105    validEnd := validStart && currentRVC || !validStart && !(isLastInPacket && !currentRVC)
106
107    val currentLastHalf = lastIsValidEnd && (isLastInPacket && !currentRVC)
108
109    insts(i) := inst
110    instsRVC(i) := isRVC(inst)
111    instsMask(i) := (if (i == 0) Mux(io.prev.valid, validEnd, validStart) else validStart)
112    instsEndMask(i) := validEnd
113    instsPC(i) := pc
114
115    val brType::isCall::isRet::Nil = brInfo(inst)
116    io.out.pd(i).isRVC := instsRVC(i)
117    io.out.pd(i).brType := brType
118    io.out.pd(i).isCall := isCall
119    io.out.pd(i).isRet := isRet
120    io.out.pd(i).excType := ExcType.notExc
121    io.out.instrs(i) := insts(i)
122    io.out.pc(i) := instsPC(i)
123
124    if (i == bankWidth-1)    { lastHalf(0) := currentLastHalf }
125    if (i == PredictWidth-1) { lastHalf(1) := currentLastHalf }
126  }
127  io.out.mask := instsMask.asUInt & mask
128  io.out.lastHalf := lastHalf.asUInt
129
130  for (i <- 0 until PredictWidth) {
131    XSDebug(true.B,
132      p"instr ${Hexadecimal(io.out.instrs(i))}, " +
133      p"mask ${Binary(instsMask(i))}, " +
134      p"endMask ${Binary(instsEndMask(i))}, " +
135      p"pc ${Hexadecimal(io.out.pc(i))}, " +
136      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
137      p"brType ${Binary(io.out.pd(i).brType)}, " +
138      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
139      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
140    )
141  }
142}
143