xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision ec4b629128e8d079c26c89cba29b20f2c77748a2) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils._
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8import xiangshan.cache._
9
10trait HasPdconst{ this: XSModule =>
11  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
12  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
13  def brInfo(instr: UInt) = {
14    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
15    val rd = Mux(isRVC(instr), instr(12), instr(11,7))
16    val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15))
17    val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64
18    val isRet = brType === BrType.jalr && isLink(rs) && !isCall
19    List(brType, isCall, isRet)
20  }
21}
22
23object BrType {
24  def notBr   = "b00".U
25  def branch  = "b01".U
26  def jal     = "b10".U
27  def jalr    = "b11".U
28  def apply() = UInt(2.W)
29}
30
31object ExcType {  //TODO:add exctype
32  def notExc = "b000".U
33  def apply() = UInt(3.W)
34}
35
36class PreDecodeInfo extends XSBundle {  // 8 bit
37  val isRVC   = Bool()
38  val brType  = UInt(2.W)
39  val isCall  = Bool()
40  val isRet   = Bool()
41  val excType = UInt(3.W)
42  def isBr = brType === BrType.branch
43  def isJal = brType === BrType.jal
44  def isJalr = brType === BrType.jalr
45  def notCFI = brType === BrType.notBr
46}
47
48class PreDecodeResp extends XSBundle with HasIFUConst {
49  val instrs = Vec(PredictWidth, UInt(32.W))
50  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
51  val mask = UInt(PredictWidth.W)
52  // one for the first bank
53  val lastHalf = Bool()
54  val pd = Vec(PredictWidth, (new PreDecodeInfo))
55}
56
57class PreDecode extends XSModule with HasPdconst with HasIFUConst {
58  val io = IO(new Bundle() {
59    val in = Input(new ICacheResp)
60    val prev = Flipped(ValidIO(UInt(16.W)))
61    val prev_pc = Input(UInt(VAddrBits.W))
62    val out = Output(new PreDecodeResp)
63  })
64
65  val data = io.in.data
66  val mask = io.in.mask
67
68  val packetAlignedPC = packetAligned(io.in.pc)
69  val packetOffset = offsetInPacket(io.in.pc)
70
71  val firstValidIdx = packetOffset // io.prev.valid should only occur with firstValidIdx = 0
72  XSError(firstValidIdx =/= 0.U && io.prev.valid && HasCExtension.B, p"pc:${io.in.pc}, mask:${io.in.mask}, prevhalfInst valid occurs on unaligned fetch packet\n")
73
74  val instsMask = Wire(Vec(PredictWidth, Bool()))
75  val instsEndMask = Wire(Vec(PredictWidth, Bool()))
76
77  val rawInsts = if (HasCExtension) {
78                   VecInit((0 until PredictWidth).map(i => if (i == PredictWidth-1) Cat(0.U(16.W), data(i*16+15, i*16))
79                                                         else data(i*16+31, i*16)))
80                 } else {
81                   VecInit((0 until PredictWidth).map(i => data(i*32+31, i*32)))
82                 }
83
84  for (i <- 0 until PredictWidth) {
85    val inst = WireInit(rawInsts(i))
86    val validStart = Wire(Bool()) // is the beginning of a valid inst
87    val validEnd = Wire(Bool())  // is the end of a valid inst
88
89    val isFirstInPacket = i.U === firstValidIdx
90    val isLastInPacket = (i == PredictWidth-1).B
91    val currentRVC = isRVC(inst) && HasCExtension.B
92
93    val lastIsValidEnd = (if (i == 0) { !io.prev.valid } else { instsEndMask(i-1) || isFirstInPacket }) || !HasCExtension.B
94
95    inst := (if (HasCExtension)
96               Mux(io.prev.valid && i.U === 0.U,
97                 Cat(rawInsts(i)(15,0), io.prev.bits),
98                 rawInsts(i))
99             else
100               rawInsts(i))
101
102    // when disable rvc, every 4 bytes should be an inst
103    validStart := lastIsValidEnd && !(isLastInPacket && !currentRVC) || !HasCExtension.B
104    validEnd := validStart && currentRVC || !validStart && !(isLastInPacket && !currentRVC) || !HasCExtension.B
105
106    val currentLastHalf = lastIsValidEnd && (isLastInPacket && !currentRVC) && HasCExtension.B
107
108    instsMask(i) := (if (i == 0) Mux(io.prev.valid, validEnd, validStart) else validStart)
109    instsEndMask(i) := validEnd
110
111    val brType::isCall::isRet::Nil = brInfo(inst)
112    io.out.pd(i).isRVC := currentRVC
113    io.out.pd(i).brType := brType
114    io.out.pd(i).isCall := isCall
115    io.out.pd(i).isRet := isRet
116    io.out.pd(i).excType := ExcType.notExc
117    io.out.instrs(i) := inst
118    io.out.pc(i) := Mux(io.prev.valid && HasCExtension.B && (i==0).B, io.prev_pc, Cat(packetIdx(io.in.pc), (i << instOffsetBits).U(log2Ceil(packetBytes).W)))
119
120    if (i == PredictWidth-1) { io.out.lastHalf := currentLastHalf }
121  }
122  io.out.mask := instsMask.asUInt & mask
123
124  for (i <- 0 until PredictWidth) {
125    XSDebug(true.B,
126      p"instr ${Hexadecimal(io.out.instrs(i))}, " +
127      p"mask ${Binary(instsMask(i))}, " +
128      p"endMask ${Binary(instsEndMask(i))}, " +
129      p"pc ${Hexadecimal(io.out.pc(i))}, " +
130      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
131      p"brType ${Binary(io.out.pd(i).brType)}, " +
132      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
133      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
134    )
135  }
136}
137