1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientStates 23import xiangshan._ 24import xiangshan.cache.mmu._ 25import utils._ 26import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 27 28class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle 29{ 30 val vaddr = UInt(VAddrBits.W) 31 def vsetIdx = get_idx(vaddr) 32} 33 34class ICacheMainPipeResp(implicit p: Parameters) extends ICacheBundle 35{ 36 val vaddr = UInt(VAddrBits.W) 37 val readData = UInt(blockBits.W) 38 val paddr = UInt(PAddrBits.W) 39 val tlbExcp = new Bundle{ 40 val pageFault = Bool() 41 val accessFault = Bool() 42 val mmio = Bool() 43 } 44} 45 46class ICacheMainPipeBundle(implicit p: Parameters) extends ICacheBundle 47{ 48 val req = Flipped(DecoupledIO(new ICacheMainPipeReq)) 49 val resp = ValidIO(new ICacheMainPipeResp) 50} 51 52class ICacheMetaReqBundle(implicit p: Parameters) extends ICacheBundle{ 53 val toIMeta = Decoupled(new ICacheReadBundle) 54 val fromIMeta = Input(new ICacheMetaRespBundle) 55} 56 57class ICacheDataReqBundle(implicit p: Parameters) extends ICacheBundle{ 58 val toIData = Decoupled(new ICacheReadBundle) 59 val fromIData = Input(new ICacheDataRespBundle) 60} 61 62class ICacheMSHRBundle(implicit p: Parameters) extends ICacheBundle{ 63 val toMSHR = Decoupled(new ICacheMissReq) 64 val fromMSHR = Flipped(ValidIO(new ICacheMissResp)) 65} 66 67class ICachePMPBundle(implicit p: Parameters) extends ICacheBundle{ 68 val req = Valid(new PMPReqBundle()) 69 val resp = Input(new PMPRespBundle()) 70} 71 72class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{ 73 val only_0_hit = Bool() 74 val only_0_miss = Bool() 75 val hit_0_hit_1 = Bool() 76 val hit_0_miss_1 = Bool() 77 val miss_0_hit_1 = Bool() 78 val miss_0_miss_1 = Bool() 79 val bank_hit = Vec(2,Bool()) 80 val hit = Bool() 81} 82 83class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle { 84 /*** internal interface ***/ 85 val metaArray = new ICacheMetaReqBundle 86 val dataArray = new ICacheDataReqBundle 87 val mshr = Vec(PortNumber, new ICacheMSHRBundle) 88 /*** outside interface ***/ 89 val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 90 val pmp = Vec(PortNumber, new ICachePMPBundle) 91 val itlb = Vec(PortNumber, new BlockTlbRequestIO) 92 val respStall = Input(Bool()) 93 val perfInfo = Output(new ICachePerfInfo) 94} 95 96class ICacheMainPipe(implicit p: Parameters) extends ICacheModule 97{ 98 val io = IO(new ICacheMainPipeInterface) 99 100 val (fromIFU, toIFU) = (io.fetch.map(_.req), io.fetch.map(_.resp)) 101 val (toMeta, metaResp) = (io.metaArray.toIMeta, io.metaArray.fromIMeta) 102 val (toData, dataResp) = (io.dataArray.toIData, io.dataArray.fromIData) 103 val (toMSHR, fromMSHR) = (io.mshr.map(_.toMSHR), io.mshr.map(_.fromMSHR)) 104 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 105 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 106 107 val s0_ready, s1_ready, s2_ready = WireInit(false.B) 108 val s0_fire, s1_fire , s2_fire = WireInit(false.B) 109 110 /** 111 ****************************************************************************** 112 * Stage 0 113 * - 114 * 115 ****************************************************************************** 116 */ 117 118 val s0_valid = fromIFU.map(_.valid).reduce(_||_) 119 val s0_req_vaddr = VecInit(fromIFU.map(_.bits.vaddr)) 120 val s0_req_vsetIdx = VecInit(fromIFU.map(_.bits.vsetIdx)) 121 val s0_only_fisrt = fromIFU(0).valid && !fromIFU(0).valid 122 val s0_double_line = fromIFU(0).valid && fromIFU(1).valid 123 124 //fetch: send addr to Meta/TLB and Data simultaneously 125 val fetch_req = List(toMeta, toData) 126 for(i <- 0 until 2) { 127 fetch_req(i).valid := s0_valid 128 fetch_req(i).bits.isDoubleLine := s0_double_line 129 fetch_req(i).bits.vSetIdx := s0_req_vsetIdx 130 } 131 132 toITLB(0).valid := s0_valid 133 toITLB(0).bits.size := 3.U // TODO: fix the size 134 toITLB(0).bits.vaddr := s0_req_vaddr(0)//addrAlign(s1_req_vaddr(0), blockBytes, VAddrBits) 135 toITLB(0).bits.debug.pc := s0_req_vaddr(0)//addrAlign(s1_req_vaddr(0), blockBytes, VAddrBits) 136 137 toITLB(1).valid := s0_valid && s0_double_line 138 toITLB(1).bits.size := 3.U // TODO: fix the size 139 toITLB(1).bits.vaddr := s0_req_vaddr(1)//addrAlign(s1_req_vaddr(1), blockBytes, VAddrBits) 140 toITLB(1).bits.debug.pc := s0_req_vaddr(1)//addrAlign(s1_req_vaddr(1), blockBytes, VAddrBits) 141 142 toITLB.map{port => 143 port.bits.cmd := TlbCmd.exec 144 port.bits.robIdx := DontCare 145 port.bits.debug.isFirstIssue := DontCare 146 } 147 148 val t_idle :: t_miss :: t_fixed :: Nil = Enum(3) 149 val tlb_status = RegInit(VecInit(Seq.fill(PortNumber)(t_idle))) 150 dontTouch(tlb_status) 151 152 val tlb_miss_vec = VecInit((0 until PortNumber).map( i => toITLB(i).valid && fromITLB(i).bits.miss )) 153 val tlb_resp = Wire(Vec(2, Bool()))//VecInit((0 until PortNumber).map( i => !fromITLB(i).bits.miss )).reduce(_&&_) 154 tlb_resp(0) := !fromITLB(0).bits.miss 155 tlb_resp(1) := !fromITLB(1).bits.miss || !s0_double_line 156 val tlb_all_resp = tlb_resp.reduce(_&&_) 157 // val tlb_miss_slot = Seq.fill(PortNumber)(RegInit(0.U.asTypeOf(new TlbResp))) 158 159 (0 until PortNumber).map { i => 160 when(tlb_miss_vec(i)){ 161 tlb_status(i) := t_miss 162 } 163 164 when(tlb_status(i) === t_miss && !fromITLB(i).bits.miss){ 165 tlb_status(i) := t_idle 166 } 167 } 168 169 s0_fire := s0_valid && s1_ready && tlb_all_resp && fetch_req(0).ready && fetch_req(1).ready 170 171 //TODO: fix GTimer() condition 172 fromIFU.map(_.ready := fetch_req(0).ready && fetch_req(1).ready && 173 tlb_all_resp && 174 s1_ready && GTimer() > 500.U ) 175 176 177// XSPerfAccumulate("ifu_bubble_ftq_not_valid", !f0_valid ) 178// XSPerfAccumulate("ifu_bubble_pipe_stall", f0_valid && fetch_req(0).ready && fetch_req(1).ready && !s1_ready ) 179// XSPerfAccumulate("ifu_bubble_sram_0_busy", f0_valid && !fetch_req(0).ready ) 180// XSPerfAccumulate("ifu_bubble_sram_1_busy", f0_valid && !fetch_req(1).ready ) 181 182 /** 183 ****************************************************************************** 184 * Stage 1 185 * - 186 * 187 ****************************************************************************** 188 */ 189 190 //TODO: handle fetch exceptions 191 192 val tlbRespAllValid = WireInit(false.B) 193 194 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = false.B, lastFlush = false.B) 195 196 val s1_req_vaddr = RegEnable(next = s0_req_vaddr, enable = s0_fire) 197 val s1_req_vsetIdx = RegEnable(next = s0_req_vsetIdx, enable = s0_fire) 198 val s1_only_fisrt = RegEnable(next = s0_only_fisrt, enable = s0_fire) 199 val s1_double_line = RegEnable(next = s0_double_line, enable = s0_fire) 200 201 s1_ready := s2_ready && tlbRespAllValid || !s1_valid 202 s1_fire := s1_valid && tlbRespAllValid && s2_ready 203 204 fromITLB.map(_.ready := true.B) 205 206 // val tlbRespValid = fromITLB.map(_.valid) 207 val s1_tlb_all_resp_wire = RegNext(s0_fire) //TODO: if there is another iTLB req source, here should have ID/address compare 208 val s1_tlb_all_resp_reg = RegInit(false.B) 209 210 when(s1_valid && s1_tlb_all_resp_wire && !s2_ready) {s1_tlb_all_resp_reg := true.B} 211 .elsewhen(s1_fire && s1_tlb_all_resp_reg) {s1_tlb_all_resp_reg := false.B} 212 213 tlbRespAllValid := s1_tlb_all_resp_wire || s1_tlb_all_resp_reg 214 215 //response 216 val tlbRespPAddr = ResultHoldBypass(valid = s1_tlb_all_resp_wire, data = VecInit(fromITLB.map(_.bits.paddr))) 217 val tlbExcpPF = ResultHoldBypass(valid = s1_tlb_all_resp_wire, data = VecInit(fromITLB.map(port => port.bits.excp.pf.instr && port.valid))) 218 val tlbExcpAF = ResultHoldBypass(valid = s1_tlb_all_resp_wire, data = VecInit(fromITLB.map(port => port.bits.excp.af.instr && port.valid))) 219 220 val s1_req_paddr = tlbRespPAddr 221 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag(_))) 222 223 val s1_meta_ptags = ResultHoldBypass(data = metaResp.tags, valid = RegNext(s0_fire)) 224 val s1_meta_cohs = ResultHoldBypass(data = metaResp.cohs, valid = RegNext(s0_fire)) 225 val s1_data_cacheline = ResultHoldBypass(data = dataResp.datas, valid = RegNext(s0_fire)) 226 227 val s1_tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === s1_req_ptags(p) )))) 228 val s1_tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(s1_tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_cohs(k)(w).isValid()}))) 229 val s1_tag_match = VecInit(s1_tag_match_vec.map(vector => ParallelOR(vector))) 230 231 val s1_port_hit = VecInit(Seq(s1_tag_match(0) && s1_valid && !tlbExcpPF(0) && !tlbExcpAF(0), s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcpPF(1) && !tlbExcpAF(1) )) 232 val s1_bank_miss = VecInit(Seq(!s1_tag_match(0) && s1_valid && !tlbExcpPF(0) && !tlbExcpAF(0), !s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcpPF(1) && !tlbExcpAF(1) )) 233 val s1_hit = (s1_port_hit(0) && s1_port_hit(1)) || (!s1_double_line && s1_port_hit(0)) 234 235 /** choose victim cacheline */ 236 val replacers = Seq.fill(PortNumber)(ReplacementPolicy.fromString(cacheParams.replacer,nWays,nSets/PortNumber)) 237 val s1_victim_oh = ResultHoldBypass(data = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(s1_req_vsetIdx(i)))}), valid = RegNext(s0_fire)) 238 239 val s1_victim_coh = VecInit(s1_victim_oh.zipWithIndex.map {case(oh, port) => Mux1H(oh, s1_meta_cohs(port))}) 240 241 assert(PopCount(s1_tag_match_vec(0)) <= 1.U && PopCount(s1_tag_match_vec(1)) <= 1.U, "Multiple hit in main pipe") 242 243 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 244 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 245 246 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 247 248 val s1_hit_data = VecInit(s1_data_cacheline.zipWithIndex.map { case(bank, i) => 249 val port_hit_data = Mux1H(s1_tag_match_vec(i).asUInt, bank) 250 port_hit_data 251 }) 252 253 (0 until nWays).map{ w => 254 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), s1_fire && s1_port_hit(0) && OHToUInt(s1_tag_match_vec(0)) === w.U) 255 } 256 257 (0 until nWays).map{ w => 258 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), s1_fire && !s1_port_hit(0) && OHToUInt(s1_victim_oh(0)) === w.U) 259 } 260 261 (0 until nWays).map{ w => 262 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && s1_port_hit(1) && OHToUInt(s1_tag_match_vec(1)) === w.U) 263 } 264 265 (0 until nWays).map{ w => 266 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && !s1_port_hit(1) && OHToUInt(s1_victim_oh(1)) === w.U) 267 } 268 269 XSPerfAccumulate("ifu_bubble_s1_tlb_miss", s1_valid && !tlbRespAllValid ) 270 271 /** 272 ****************************************************************************** 273 * Stage 2 274 * - 275 * 276 ****************************************************************************** 277 */ 278 val s2_fetch_finish = Wire(Bool()) 279 280 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = false.B, lastFlush = false.B) 281 val s2_miss_available = Wire(Bool()) 282 283 s2_ready := (s2_valid && s2_fetch_finish && !io.respStall) || (!s2_valid && s2_miss_available) 284 s2_fire := s2_valid && s2_fetch_finish && !io.respStall 285 286 val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 287 288 val (s2_req_paddr , s2_req_vaddr) = (RegEnable(next = s1_req_paddr, enable = s1_fire), RegEnable(next = s1_req_vaddr, enable = s1_fire)) 289 val s2_req_vsetIdx = RegEnable(next = s1_req_vsetIdx, enable = s1_fire) 290 val s2_req_ptags = RegEnable(next = s1_req_ptags, enable = s1_fire) 291 val s2_only_fisrt = RegEnable(next = s1_only_fisrt, enable = s1_fire) 292 val s2_double_line = RegEnable(next = s1_double_line, enable = s1_fire) 293 val s2_hit = RegEnable(next = s1_hit , enable = s1_fire) 294 val s2_port_hit = RegEnable(next = s1_port_hit, enable = s1_fire) 295 val s2_bank_miss = RegEnable(next = s1_bank_miss, enable = s1_fire) 296 297 298 val sec_meet_vec = Wire(Vec(2, Bool())) 299 val s2_fixed_hit_vec = VecInit((0 until 2).map(i => s2_port_hit(i) || sec_meet_vec(i))) 300 val s2_fixed_hit = (s2_valid && s2_fixed_hit_vec(0) && s2_fixed_hit_vec(1) && s2_double_line) || (s2_valid && s2_fixed_hit_vec(0) && !s2_double_line) 301 302 //replacement 303 val s2_waymask = RegEnable(next = s1_victim_oh, enable = s1_fire) 304 val s2_victim_coh = RegEnable(next = s1_victim_coh, enable = s1_fire) 305 306 /** exception and pmp logic **/ 307 //PMP Result 308 val pmpExcpAF = Wire(Vec(PortNumber, Bool())) 309 pmpExcpAF(0) := fromPMP(0).instr 310 pmpExcpAF(1) := fromPMP(1).instr && s2_double_line 311 //exception information 312 val s2_except_pf = RegEnable(next =tlbExcpPF, enable = s1_fire) 313 val s2_except_af = VecInit(RegEnable(next = tlbExcpAF, enable = s1_fire).zip(pmpExcpAF).map(a => a._1 || DataHoldBypass(a._2, RegNext(s1_fire)).asBool)) 314 val s2_except = VecInit((0 until 2).map{i => s2_except_pf(i) || s2_except_af(i)}) 315 val s2_has_except = s2_valid && (s2_except_af.reduce(_||_) || s2_except_pf.reduce(_||_)) 316 //MMIO 317 val s2_mmio = DataHoldBypass(io.pmp(0).resp.mmio && !s2_except_af(0) && !s2_except_pf(0), RegNext(s1_fire)).asBool() 318 319 io.pmp.zipWithIndex.map { case (p, i) => 320 p.req.valid := s2_fire 321 p.req.bits.addr := s2_req_paddr(i) 322 p.req.bits.size := 3.U // TODO 323 p.req.bits.cmd := TlbCmd.exec 324 } 325 326 /*** cacheline miss logic ***/ 327 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: Nil = Enum(8) 328 val wait_state = RegInit(wait_idle) 329 330 val port_miss_fix = VecInit(Seq(fromMSHR(0).fire() && !s2_port_hit(0), fromMSHR(1).fire() && s2_double_line && !s2_port_hit(1) )) 331 332 class MissSlot(implicit p: Parameters) extends ICacheBundle { 333 val m_vSetIdx = UInt(idxBits.W) 334 val m_pTag = UInt(tagBits.W) 335 val m_data = UInt(blockBits.W) 336 } 337 338 val missSlot = Seq.fill(2)(RegInit(0.U.asTypeOf(new MissSlot))) 339 val m_invalid :: m_valid :: m_refilled :: m_flushed :: m_wait_sec_miss :: m_check_final ::Nil = Enum(6) 340 val missStateQueue = RegInit(VecInit(Seq.fill(2)(m_invalid)) ) 341 val reservedRefillData = Wire(Vec(2, UInt(blockBits.W))) 342 343 s2_miss_available := VecInit(missStateQueue.map(entry => entry === m_invalid || entry === m_wait_sec_miss)).reduce(_&&_) 344 345 val fix_sec_miss = Wire(Vec(4, Bool())) 346 val sec_meet_0_miss = fix_sec_miss(0) || fix_sec_miss(2) 347 val sec_meet_1_miss = fix_sec_miss(1) || fix_sec_miss(3) 348 sec_meet_vec := VecInit(Seq(sec_meet_0_miss,sec_meet_1_miss )) 349 350 /*** miss/hit pattern: <Control Signal> only raise at the first cycle of s2_valid ***/ 351 val cacheline_0_hit = (s2_port_hit(0) || sec_meet_0_miss) 352 val cacheline_0_miss = !s2_port_hit(0) && !sec_meet_0_miss 353 354 val cacheline_1_hit = (s2_port_hit(1) || sec_meet_1_miss) 355 val cacheline_1_miss = !s2_port_hit(1) && !sec_meet_1_miss 356 357 val only_0_miss = RegNext(s1_fire) && cacheline_0_miss && !s2_double_line && !s2_has_except && !s2_mmio 358 val only_0_hit = RegNext(s1_fire) && cacheline_0_hit && !s2_double_line && !s2_mmio 359 val hit_0_hit_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_hit && s2_double_line && !s2_mmio 360 val hit_0_miss_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 361 val miss_0_hit_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_hit && s2_double_line && !s2_has_except && !s2_mmio 362 val miss_0_miss_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 363 364 val hit_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_hit 365 val miss_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_miss 366 val except_0 = RegNext(s1_fire) && s2_except(0) 367 368 def holdReleaseLatch(valid: Bool, release: Bool, flush: Bool): Bool ={ 369 val bit = RegInit(false.B) 370 when(flush) { bit := false.B } 371 .elsewhen(valid && !release) { bit := true.B } 372 .elsewhen(release) { bit := false.B} 373 bit || valid 374 } 375 376 /*** miss/hit pattern latch: <Control Signal> latch the miss/hit patter if pipeline stop ***/ 377 val miss_0_hit_1_latch = holdReleaseLatch(valid = miss_0_hit_1, release = s2_fire, flush = false.B) 378 val miss_0_miss_1_latch = holdReleaseLatch(valid = miss_0_miss_1, release = s2_fire, flush = false.B) 379 val only_0_miss_latch = holdReleaseLatch(valid = only_0_miss, release = s2_fire, flush = false.B) 380 val hit_0_miss_1_latch = holdReleaseLatch(valid = hit_0_miss_1, release = s2_fire, flush = false.B) 381 382 val miss_0_except_1_latch = holdReleaseLatch(valid = miss_0_except_1, release = s2_fire, flush = false.B) 383 val except_0_latch = holdReleaseLatch(valid = except_0, release = s2_fire, flush = false.B) 384 val hit_0_except_1_latch = holdReleaseLatch(valid = hit_0_except_1, release = s2_fire, flush = false.B) 385 386 val only_0_hit_latch = holdReleaseLatch(valid = only_0_hit, release = s2_fire, flush = false.B) 387 val hit_0_hit_1_latch = holdReleaseLatch(valid = hit_0_hit_1, release = s2_fire, flush = false.B) 388 389 390 def waitSecondComeIn(missState: UInt): Bool = (missState === m_wait_sec_miss) 391 392 /*** deal with secondary miss when s1 enter f2 ***/ 393 def getMissSituat(slotNum : Int, missNum : Int ) :Bool = { 394 RegNext(s1_fire) && (missSlot(slotNum).m_vSetIdx === s2_req_vsetIdx(missNum)) && (missSlot(slotNum).m_pTag === s2_req_ptags(missNum)) && !s2_port_hit(missNum) && waitSecondComeIn(missStateQueue(slotNum)) && !s2_mmio 395 } 396 397 val miss_0_s2_0 = getMissSituat(slotNum = 0, missNum = 0) 398 val miss_0_s2_1 = getMissSituat(slotNum = 0, missNum = 1) 399 val miss_1_s2_0 = getMissSituat(slotNum = 1, missNum = 0) 400 val miss_1_s2_1 = getMissSituat(slotNum = 1, missNum = 1) 401 402 val miss_0_s2_0_latch = holdReleaseLatch(valid = miss_0_s2_0, release = s2_fire, flush = false.B) 403 val miss_0_s2_1_latch = holdReleaseLatch(valid = miss_0_s2_1, release = s2_fire, flush = false.B) 404 val miss_1_s2_0_latch = holdReleaseLatch(valid = miss_1_s2_0, release = s2_fire, flush = false.B) 405 val miss_1_s2_1_latch = holdReleaseLatch(valid = miss_1_s2_1, release = s2_fire, flush = false.B) 406 407 408 val slot_0_solve = fix_sec_miss(0) || fix_sec_miss(1) 409 val slot_1_solve = fix_sec_miss(2) || fix_sec_miss(3) 410 val slot_slove = VecInit(Seq(slot_0_solve, slot_1_solve)) 411 412 fix_sec_miss := VecInit(Seq(miss_0_s2_0_latch, miss_0_s2_1_latch, miss_1_s2_0_latch, miss_1_s2_1_latch)) 413 414 reservedRefillData(0) := DataHoldBypass(data = missSlot(0).m_data, valid = miss_0_s2_0 || miss_0_s2_1) 415 reservedRefillData(1) := DataHoldBypass(data = missSlot(1).m_data, valid = miss_1_s2_0 || miss_1_s2_1) 416 417 switch(wait_state){ 418 is(wait_idle){ 419 when(miss_0_except_1_latch){ 420 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 421 }.elsewhen( only_0_miss_latch || miss_0_hit_1_latch){ 422 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 423 }.elsewhen(hit_0_miss_1_latch){ 424 wait_state := Mux(toMSHR(1).ready, wait_queue_ready ,wait_idle ) 425 }.elsewhen( miss_0_miss_1_latch ){ 426 wait_state := Mux(toMSHR(0).ready && toMSHR(1).ready, wait_queue_ready ,wait_idle) 427 } 428 } 429 430 is(wait_queue_ready){ 431 wait_state := wait_send_req 432 } 433 434 is(wait_send_req) { 435 when(miss_0_except_1_latch || only_0_miss_latch || hit_0_miss_1_latch || miss_0_hit_1_latch){ 436 wait_state := wait_one_resp 437 }.elsewhen( miss_0_miss_1_latch ){ 438 wait_state := wait_two_resp 439 } 440 } 441 442 is(wait_one_resp) { 443 when( (miss_0_except_1_latch ||only_0_miss_latch || miss_0_hit_1_latch) && fromMSHR(0).fire()){ 444 wait_state := wait_finish 445 }.elsewhen( hit_0_miss_1_latch && fromMSHR(1).fire()){ 446 wait_state := wait_finish 447 } 448 } 449 450 is(wait_two_resp) { 451 when(fromMSHR(0).fire() && fromMSHR(1).fire()){ 452 wait_state := wait_finish 453 }.elsewhen( !fromMSHR(0).fire() && fromMSHR(1).fire() ){ 454 wait_state := wait_0_resp 455 }.elsewhen(fromMSHR(0).fire() && !fromMSHR(1).fire()){ 456 wait_state := wait_1_resp 457 } 458 } 459 460 is(wait_0_resp) { 461 when(fromMSHR(0).fire()){ 462 wait_state := wait_finish 463 } 464 } 465 466 is(wait_1_resp) { 467 when(fromMSHR(1).fire()){ 468 wait_state := wait_finish 469 } 470 } 471 472 is(wait_finish) {when(s2_fire) {wait_state := wait_idle } 473 } 474 } 475 476 477 (0 until 2).map { i => 478 if(i == 1) toMSHR(i).valid := (hit_0_miss_1_latch || miss_0_miss_1_latch) && wait_state === wait_queue_ready && !s2_mmio 479 else toMSHR(i).valid := (only_0_miss_latch || miss_0_hit_1_latch || miss_0_miss_1_latch || miss_0_except_1_latch) && wait_state === wait_queue_ready && !s2_mmio 480 toMSHR(i).bits.paddr := s2_req_paddr(i) 481 toMSHR(i).bits.vaddr := s2_req_vaddr(i) 482 toMSHR(i).bits.waymask := s2_waymask(i) 483 toMSHR(i).bits.coh := s2_victim_coh(i) 484 485 486 when(toMSHR(i).fire() && missStateQueue(i) === m_invalid){ 487 missStateQueue(i) := m_valid 488 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 489 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 490 } 491 492 when(fromMSHR(i).fire() && missStateQueue(i) === m_valid ){ 493 missStateQueue(i) := m_refilled 494 missSlot(i).m_data := fromMSHR(i).bits.data 495 } 496 497 498 when(s2_fire && missStateQueue(i) === m_refilled){ 499 missStateQueue(i) := m_wait_sec_miss 500 } 501 502 /*** Only the first cycle to check whether meet the secondary miss ***/ 503 when(missStateQueue(i) === m_wait_sec_miss){ 504 /*** The seondary req has been fix by this slot and another also hit || the secondary req for other cacheline and hit ***/ 505 when((slot_slove(i) && s2_fire) || (!slot_slove(i) && s2_fire) ) { 506 missStateQueue(i) := m_invalid 507 } 508 /*** The seondary req has been fix by this slot but another miss/f3 not ready || the seondary req for other cacheline and miss ***/ 509 .elsewhen((slot_slove(i) && !s2_fire && s2_valid) || (s2_valid && !slot_slove(i) && !s2_fire) ){ 510 missStateQueue(i) := m_check_final 511 } 512 } 513 514 when(missStateQueue(i) === m_check_final && toMSHR(i).fire()){ 515 missStateQueue(i) := m_valid 516 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 517 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 518 }.elsewhen(missStateQueue(i) === m_check_final) { 519 missStateQueue(i) := m_invalid 520 } 521 } 522 523 val miss_all_fix = wait_state === wait_finish 524 s2_fetch_finish := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch || s2_mmio) 525 526 XSPerfAccumulate("ifu_bubble_s2_miss", s2_valid && !s2_fetch_finish ) 527 528 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 529 t_s(0) := s1_req_vsetIdx(i) 530 t_w(0).valid := s1_port_hit(i) 531 t_w(0).bits := OHToUInt(s1_tag_match_vec(i)) 532 533 t_s(1) := s2_req_vsetIdx(i) 534 t_w(1).valid := s2_valid && !s2_port_hit(i) 535 t_w(1).bits := OHToUInt(s2_waymask(i)) 536 } 537 538 val s2_hit_datas = RegEnable(next = s1_hit_data, enable = s1_fire) 539 val s2_datas = Wire(Vec(2, UInt(blockBits.W))) 540 541 s2_datas.zipWithIndex.map{case(bank,i) => 542 if(i == 0) bank := Mux(s2_port_hit(i), s2_hit_datas(i),Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data))) 543 else bank := Mux(s2_port_hit(i), s2_hit_datas(i),Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data))) 544 } 545 546 547 (0 until PortNumber).map{ i => 548 if(i ==0) toIFU(i).valid := s2_fire 549 else toIFU(i).valid := s2_fire && s2_double_line 550 toIFU(i).bits.readData := s2_datas(i) 551 toIFU(i).bits.paddr := s2_req_paddr(i) 552 toIFU(i).bits.vaddr := s2_req_vaddr(i) 553 toIFU(i).bits.tlbExcp.pageFault := s2_except_pf(i) 554 toIFU(i).bits.tlbExcp.accessFault := s2_except_af(i) 555 toIFU(i).bits.tlbExcp.mmio := s2_mmio 556 } 557 558 io.perfInfo.only_0_hit := only_0_miss_latch 559 io.perfInfo.only_0_miss := only_0_miss_latch 560 io.perfInfo.hit_0_hit_1 := hit_0_hit_1_latch 561 io.perfInfo.hit_0_miss_1 := hit_0_miss_1_latch 562 io.perfInfo.miss_0_hit_1 := miss_0_hit_1_latch 563 io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch 564 io.perfInfo.bank_hit(0) := only_0_miss_latch || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch 565 io.perfInfo.bank_hit(1) := miss_0_hit_1_latch || hit_0_hit_1_latch 566 io.perfInfo.hit := hit_0_hit_1_latch 567} 568