1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest._ 23import freechips.rocketchip.tilelink._ 24import utils._ 25import xiangshan.cache.mmu._ 26import xiangshan.frontend._ 27import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 28import huancun.PreferCacheKey 29import xiangshan.XSCoreParamsKey 30import utility._ 31 32abstract class IPrefetchBundle(implicit p: Parameters) extends ICacheBundle 33abstract class IPrefetchModule(implicit p: Parameters) extends ICacheModule 34 35class IPrefetchIO(implicit p: Parameters) extends IPrefetchBundle { 36 // control 37 val csr_pf_enable = Input(Bool()) 38 val csr_parity_enable = Input(Bool()) 39 val flush = Input(Bool()) 40 41 val ftqReq = Flipped(new FtqToPrefetchIO) 42 val itlb = Vec(PortNumber, new TlbRequestIO) 43 val pmp = Vec(PortNumber, new ICachePMPBundle) 44 val metaRead = new ICacheMetaReqBundle 45 val MSHRReq = DecoupledIO(new ICacheMissReq) 46 val MSHRResp = Flipped(ValidIO(new ICacheMissResp)) 47 val wayLookupWrite = DecoupledIO(new WayLookupInfo) 48} 49 50class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule 51{ 52 val io: IPrefetchIO = IO(new IPrefetchIO) 53 54 val fromFtq = io.ftqReq 55 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 56 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 57 val (toMeta, fromMeta) = (io.metaRead.toIMeta, io.metaRead.fromIMeta) 58 val (toMSHR, fromMSHR) = (io.MSHRReq, io.MSHRResp) 59 val toWayLookup = io.wayLookupWrite 60 61 // FIXME: csr_pf_enable/enableBit is not used now 62 val enableBit = RegInit(false.B) 63 enableBit := io.csr_pf_enable 64 65 val s0_fire, s1_fire, s2_fire = WireInit(false.B) 66 val s0_discard, s2_discard = WireInit(false.B) 67 val s0_ready, s1_ready, s2_ready = WireInit(false.B) 68 val s0_flush, s1_flush, s2_flush = WireInit(false.B) 69 val from_bpu_s0_flush, from_bpu_s1_flush = WireInit(false.B) 70 71 /** 72 ****************************************************************************** 73 * IPrefetch Stage 0 74 * - 1. receive ftq req 75 * - 2. send req to ITLB 76 * - 3. send req to Meta SRAM 77 ****************************************************************************** 78 */ 79 val s0_valid = fromFtq.req.valid 80 81 /** 82 ****************************************************************************** 83 * receive ftq req 84 ****************************************************************************** 85 */ 86 val s0_req_vaddr = VecInit(Seq(fromFtq.req.bits.startAddr, fromFtq.req.bits.nextlineStart)) 87 val s0_req_ftqIdx = fromFtq.req.bits.ftqIdx 88 val s0_doubleline = fromFtq.req.bits.crossCacheline 89 val s0_req_vSetIdx = s0_req_vaddr.map(get_idx) 90 91 from_bpu_s0_flush := fromFtq.flushFromBpu.shouldFlushByStage2(s0_req_ftqIdx) || 92 fromFtq.flushFromBpu.shouldFlushByStage3(s0_req_ftqIdx) 93 s0_flush := io.flush || from_bpu_s0_flush || s1_flush 94 95 val s0_can_go = s1_ready && toITLB(0).ready && toITLB(1).ready && toMeta.ready 96 fromFtq.req.ready := s0_can_go 97 98 s0_fire := s0_valid && s0_can_go && !s0_flush 99 100 /** 101 ****************************************************************************** 102 * IPrefetch Stage 1 103 * - 1. Receive resp from ITLB 104 * - 2. Receive resp from IMeta and check 105 * - 3. Monitor the requests from missUnit to write to SRAM. 106 * - 4. Wirte wayLookup 107 ****************************************************************************** 108 */ 109 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = s1_flush, lastFlush = false.B) 110 111 val s1_req_vaddr = RegEnable(s0_req_vaddr, 0.U.asTypeOf(s0_req_vaddr), s0_fire) 112 val s1_doubleline = RegEnable(s0_doubleline, 0.U.asTypeOf(s0_doubleline), s0_fire) 113 val s1_req_ftqIdx = RegEnable(s0_req_ftqIdx, 0.U.asTypeOf(s0_req_ftqIdx), s0_fire) 114 val s1_req_vSetIdx = VecInit(s1_req_vaddr.map(get_idx)) 115 116 val m_idle :: m_itlbResend :: m_metaResend :: m_enqWay :: m_enterS2 :: Nil = Enum(5) 117 val state = RegInit(m_idle) 118 val next_state = WireDefault(state) 119 val s0_fire_r = RegNext(s0_fire) 120 dontTouch(state) 121 dontTouch(next_state) 122 state := next_state 123 124 /** 125 ****************************************************************************** 126 * resend itlb req if miss 127 ****************************************************************************** 128 */ 129 val s1_wait_itlb = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 130 (0 until PortNumber).foreach { i => 131 when(s1_flush) { 132 s1_wait_itlb(i) := false.B 133 }.elsewhen(RegNext(s0_fire) && fromITLB(i).bits.miss) { 134 s1_wait_itlb(i) := true.B 135 }.elsewhen(s1_wait_itlb(i) && !fromITLB(i).bits.miss) { 136 s1_wait_itlb(i) := false.B 137 } 138 } 139 val s1_need_itlb = VecInit(Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && fromITLB(0).bits.miss, 140 (RegNext(s0_fire) || s1_wait_itlb(1)) && fromITLB(1).bits.miss && s1_doubleline)) 141 val tlb_valid_pulse = VecInit(Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && !fromITLB(0).bits.miss, 142 (RegNext(s0_fire) || s1_wait_itlb(1)) && !fromITLB(1).bits.miss && s1_doubleline)) 143 val tlb_valid_latch = VecInit((0 until PortNumber).map(i => ValidHoldBypass(tlb_valid_pulse(i), s1_fire, flush=s1_flush))) 144 val itlb_finish = tlb_valid_latch(0) && (!s1_doubleline || tlb_valid_latch(1)) 145 146 for (i <- 0 until PortNumber) { 147 toITLB(i).valid := s1_need_itlb(i) || (s0_valid && (if(i == 0) true.B else s0_doubleline)) 148 toITLB(i).bits := DontCare 149 toITLB(i).bits.size := 3.U 150 toITLB(i).bits.vaddr := Mux(s1_need_itlb(i), s1_req_vaddr(i), s0_req_vaddr(i)) 151 toITLB(i).bits.debug.pc := Mux(s1_need_itlb(i), s1_req_vaddr(i), s0_req_vaddr(i)) 152 toITLB(i).bits.cmd := TlbCmd.exec 153 toITLB(i).bits.no_translate := false.B 154 } 155 fromITLB.foreach(_.ready := true.B) 156 io.itlb.foreach(_.req_kill := false.B) 157 158 /** 159 ****************************************************************************** 160 * Receive resp from ITLB 161 ****************************************************************************** 162 */ 163 val s1_req_paddr_wire = VecInit(fromITLB.map(_.bits.paddr(0))) 164 val s1_req_paddr_reg = VecInit((0 until PortNumber).map( i => 165 RegEnable(s1_req_paddr_wire(i), 0.U(PAddrBits.W), tlb_valid_pulse(i)) 166 )) 167 val s1_req_paddr = VecInit((0 until PortNumber).map( i => 168 Mux(tlb_valid_pulse(i), s1_req_paddr_wire(i), s1_req_paddr_reg(i)) 169 )) 170 val s1_req_gpaddr_tmp = VecInit((0 until PortNumber).map( i => 171 ResultHoldBypass(valid = tlb_valid_pulse(i), init = 0.U.asTypeOf(fromITLB(i).bits.gpaddr(0)), data = fromITLB(i).bits.gpaddr(0)) 172 )) 173 val s1_itlb_exception = VecInit((0 until PortNumber).map( i => 174 ResultHoldBypass(valid = tlb_valid_pulse(i), init = 0.U(ExceptionType.width.W), data = ExceptionType.fromTlbResp(fromITLB(i).bits)) 175 )) 176 val s1_itlb_exception_gpf = VecInit(s1_itlb_exception.map(_ === ExceptionType.gpf)) 177 178 /* Select gpaddr with the first gpf 179 * Note: the backend wants the base guest physical address of a fetch block 180 * for port(i), its base gpaddr is actually (gpaddr - i * blocksize) 181 * see GPAMem: https://github.com/OpenXiangShan/XiangShan/blob/344cf5d55568dd40cd658a9ee66047a505eeb504/src/main/scala/xiangshan/backend/GPAMem.scala#L33-L34 182 * see also: https://github.com/OpenXiangShan/XiangShan/blob/344cf5d55568dd40cd658a9ee66047a505eeb504/src/main/scala/xiangshan/frontend/IFU.scala#L374-L375 183 */ 184 val s1_req_gpaddr = PriorityMuxDefault( 185 s1_itlb_exception_gpf zip (0 until PortNumber).map(i => s1_req_gpaddr_tmp(i) - (i << blockOffBits).U), 186 0.U.asTypeOf(s1_req_gpaddr_tmp(0)) 187 ) 188 189 /** 190 ****************************************************************************** 191 * resend metaArray read req when itlb miss finish 192 ****************************************************************************** 193 */ 194 val s1_need_meta = ((state === m_itlbResend) && itlb_finish) || (state === m_metaResend) 195 toMeta.valid := s1_need_meta || s0_valid 196 toMeta.bits := DontCare 197 toMeta.bits.isDoubleLine := Mux(s1_need_meta, s1_doubleline, s0_doubleline) 198 199 for (i <- 0 until PortNumber) { 200 toMeta.bits.vSetIdx(i) := Mux(s1_need_meta, s1_req_vSetIdx(i), s0_req_vSetIdx(i)) 201 } 202 203 /** 204 ****************************************************************************** 205 * Receive resp from IMeta and check 206 ****************************************************************************** 207 */ 208 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag)) 209 210 val s1_meta_ptags = fromMeta.tags 211 val s1_meta_valids = fromMeta.entryValid 212 // If error is found in either way, the tag_eq_vec is unreliable, so we do not use waymask, but directly .orR 213 val s1_meta_corrupt = VecInit(fromMeta.errors.map(_.asUInt.orR)) 214 215 def get_waymask(paddrs: Vec[UInt]): Vec[UInt] = { 216 val ptags = paddrs.map(get_phy_tag) 217 val tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === ptags(p))))) 218 val tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_valids(k)(w)}))) 219 val waymasks = VecInit(tag_match_vec.map(_.asUInt)) 220 waymasks 221 } 222 223 val s1_SRAM_waymasks = VecInit((0 until PortNumber).map(i => 224 Mux(tlb_valid_pulse(i), get_waymask(s1_req_paddr_wire)(i), get_waymask(s1_req_paddr_reg)(i)))) 225 226 /** 227 ****************************************************************************** 228 * update waymask according to MSHR update data 229 ****************************************************************************** 230 */ 231 def update_waymask(mask: UInt, vSetIdx: UInt, ptag: UInt): UInt = { 232 require(mask.getWidth == nWays) 233 val new_mask = WireInit(mask) 234 val valid = fromMSHR.valid && !fromMSHR.bits.corrupt 235 val vset_same = fromMSHR.bits.vSetIdx === vSetIdx 236 val ptag_same = getPhyTagFromBlk(fromMSHR.bits.blkPaddr) === ptag 237 val way_same = fromMSHR.bits.waymask === mask 238 when(valid && vset_same) { 239 when(ptag_same) { 240 new_mask := fromMSHR.bits.waymask 241 }.elsewhen(way_same) { 242 new_mask := 0.U 243 } 244 } 245 new_mask 246 } 247 248 val s1_SRAM_valid = s0_fire_r || RegNext(s1_need_meta && toMeta.ready) 249 val s1_MSHR_valid = fromMSHR.valid && !fromMSHR.bits.corrupt 250 val s1_waymasks = WireInit(VecInit(Seq.fill(PortNumber)(0.U(nWays.W)))) 251 val s1_waymasks_r = RegEnable(s1_waymasks, 0.U.asTypeOf(s1_waymasks), s1_SRAM_valid || s1_MSHR_valid) 252 (0 until PortNumber).foreach{i => 253 val old_waymask = Mux(s1_SRAM_valid, s1_SRAM_waymasks(i), s1_waymasks_r(i)) 254 s1_waymasks(i) := update_waymask(old_waymask, s1_req_vSetIdx(i), s1_req_ptags(i)) 255 } 256 257 /** 258 ****************************************************************************** 259 * send enqueu req to WayLookup 260 ******** ********************************************************************** 261 */ 262 // Disallow enqueuing wayLookup when SRAM write occurs. 263 toWayLookup.valid := ((state === m_enqWay) || ((state === m_idle) && itlb_finish)) && !s1_flush && !fromMSHR.valid 264 toWayLookup.bits.vSetIdx := s1_req_vSetIdx 265 toWayLookup.bits.waymask := s1_waymasks 266 toWayLookup.bits.ptag := s1_req_ptags 267 toWayLookup.bits.gpaddr := s1_req_gpaddr 268 (0 until PortNumber).foreach { i => 269 val excpValid = (if (i == 0) true.B else s1_doubleline) // exception in first line is always valid, in second line is valid iff is doubleline request 270 // Send s1_itlb_exception to WayLookup (instead of s1_exception_out) for better timing. Will check pmp again in mainPipe 271 toWayLookup.bits.itlb_exception(i) := Mux(excpValid, s1_itlb_exception(i), ExceptionType.none) 272 toWayLookup.bits.meta_corrupt(i) := excpValid && s1_meta_corrupt(i) 273 } 274 275 val s1_waymasks_vec = s1_waymasks.map(_.asTypeOf(Vec(nWays, Bool()))) 276 when(toWayLookup.fire) { 277 assert(PopCount(s1_waymasks_vec(0)) <= 1.U && (PopCount(s1_waymasks_vec(1)) <= 1.U || !s1_doubleline), 278 "Multiple hit in main pipe, port0:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x port1:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x ", 279 PopCount(s1_waymasks_vec(0)) > 1.U, s1_req_ptags(0), get_idx(s1_req_vaddr(0)), s1_req_vaddr(0), 280 PopCount(s1_waymasks_vec(1)) > 1.U && s1_doubleline, s1_req_ptags(1), get_idx(s1_req_vaddr(1)), s1_req_vaddr(1)) 281 } 282 283 /** 284 ****************************************************************************** 285 * PMP check 286 ****************************************************************************** 287 */ 288 toPMP.zipWithIndex.foreach { case (p, i) => 289 // if itlb has exception, paddr can be invalid, therefore pmp check can be skipped 290 p.valid := s1_valid // && s1_itlb_exception === ExceptionType.none 291 p.bits.addr := s1_req_paddr(i) 292 p.bits.size := 3.U // TODO 293 p.bits.cmd := TlbCmd.exec 294 } 295 val s1_pmp_exception = VecInit(fromPMP.map(ExceptionType.fromPMPResp)) 296 val s1_mmio = VecInit(fromPMP.map(_.mmio)) 297 298 // also raise af when meta array corrupt is detected, to cancel prefetch 299 val s1_meta_exception = VecInit(s1_meta_corrupt.map(ExceptionType.fromECC(io.csr_parity_enable, _))) 300 301 // merge s1 itlb/pmp/meta exceptions, itlb has the highest priority, pmp next, meta lowest 302 val s1_exception_out = ExceptionType.merge( 303 s1_itlb_exception, 304 s1_pmp_exception, 305 s1_meta_exception 306 ) 307 308 /** 309 ****************************************************************************** 310 * state machine 311 ******** ********************************************************************** 312 */ 313 314 switch(state) { 315 is(m_idle) { 316 when(s1_valid && !itlb_finish) { 317 next_state := m_itlbResend 318 }.elsewhen(s1_valid && itlb_finish && !toWayLookup.fire) { 319 next_state := m_enqWay 320 }.elsewhen(s1_valid && itlb_finish && toWayLookup.fire && !s2_ready) { 321 next_state := m_enterS2 322 } 323 } 324 is(m_itlbResend) { 325 when(itlb_finish && !toMeta.ready) { 326 next_state := m_metaResend 327 }.elsewhen(itlb_finish && toMeta.ready) { 328 next_state := m_enqWay 329 } 330 } 331 is(m_metaResend) { 332 when(toMeta.ready) { 333 next_state := m_enqWay 334 } 335 } 336 is(m_enqWay) { 337 when(toWayLookup.fire && !s2_ready) { 338 next_state := m_enterS2 339 }.elsewhen(toWayLookup.fire && s2_ready) { 340 next_state := m_idle 341 } 342 } 343 is(m_enterS2) { 344 when(s2_ready) { 345 next_state := m_idle 346 } 347 } 348 } 349 350 when(s1_flush) { 351 next_state := m_idle 352 } 353 354 /** Stage 1 control */ 355 from_bpu_s1_flush := s1_valid && fromFtq.flushFromBpu.shouldFlushByStage3(s1_req_ftqIdx) 356 s1_flush := io.flush || from_bpu_s1_flush 357 358 s1_ready := next_state === m_idle 359 s1_fire := (next_state === m_idle) && s1_valid && !s1_flush 360 361 /** 362 ****************************************************************************** 363 * IPrefetch Stage 2 364 * - 1. Monitor the requests from missUnit to write to SRAM. 365 * - 2. send req to missUnit 366 ****************************************************************************** 367 */ 368 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = s2_flush, lastFlush = false.B) 369 370 val s2_req_vaddr = RegEnable(s1_req_vaddr, 0.U.asTypeOf(s1_req_vaddr), s1_fire) 371 val s2_doubleline = RegEnable(s1_doubleline, 0.U.asTypeOf(s1_doubleline), s1_fire) 372 val s2_req_paddr = RegEnable(s1_req_paddr, 0.U.asTypeOf(s1_req_paddr), s1_fire) 373 val s2_exception = RegEnable(s1_exception_out, 0.U.asTypeOf(s1_exception_out), s1_fire) // includes itlb/pmp/meta exception 374 val s2_mmio = RegEnable(s1_mmio, 0.U.asTypeOf(s1_mmio), s1_fire) 375 val s2_waymasks = RegEnable(s1_waymasks, 0.U.asTypeOf(s1_waymasks), s1_fire) 376 377 val s2_req_vSetIdx = s2_req_vaddr.map(get_idx) 378 val s2_req_ptags = s2_req_paddr.map(get_phy_tag) 379 380 /** 381 ****************************************************************************** 382 * Monitor the requests from missUnit to write to SRAM 383 ****************************************************************************** 384 */ 385 386 /* NOTE: If fromMSHR.bits.corrupt, we should set s2_MSHR_hits to false.B, and send prefetch requests again. 387 * This is the opposite of how mainPipe handles fromMSHR.bits.corrupt, 388 * in which we should set s2_MSHR_hits to true.B, and send error to ifu. 389 */ 390 val s2_MSHR_match = VecInit((0 until PortNumber).map(i => 391 (s2_req_vSetIdx(i) === fromMSHR.bits.vSetIdx) && 392 (s2_req_ptags(i) === getPhyTagFromBlk(fromMSHR.bits.blkPaddr)) && 393 s2_valid && fromMSHR.valid && !fromMSHR.bits.corrupt 394 )) 395 val s2_MSHR_hits = (0 until PortNumber).map(i => ValidHoldBypass(s2_MSHR_match(i), s2_fire || s2_flush)) 396 397 val s2_SRAM_hits = s2_waymasks.map(_.orR) 398 val s2_hits = VecInit((0 until PortNumber).map(i => s2_MSHR_hits(i) || s2_SRAM_hits(i))) 399 400 /* s2_exception includes itlb pf/gpf/af, pmp af and meta corruption (af), neither of which should be prefetched 401 * mmio should not be prefetched 402 * also, if previous has exception, latter port should also not be prefetched 403 */ 404 val s2_miss = VecInit((0 until PortNumber).map { i => 405 !s2_hits(i) && (if (i==0) true.B else s2_doubleline) && 406 s2_exception.take(i+1).map(_ === ExceptionType.none).reduce(_&&_) && 407 s2_mmio.take(i+1).map(!_).reduce(_&&_) 408 }) 409 410 /** 411 ****************************************************************************** 412 * send req to missUnit 413 ****************************************************************************** 414 */ 415 val toMSHRArbiter = Module(new Arbiter(new ICacheMissReq, PortNumber)) 416 417 // To avoid sending duplicate requests. 418 val has_send = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 419 (0 until PortNumber).foreach{ i => 420 when(s1_fire) { 421 has_send(i) := false.B 422 }.elsewhen(toMSHRArbiter.io.in(i).fire) { 423 has_send(i) := true.B 424 } 425 } 426 427 (0 until PortNumber).map{ i => 428 toMSHRArbiter.io.in(i).valid := s2_valid && s2_miss(i) && !has_send(i) 429 toMSHRArbiter.io.in(i).bits.blkPaddr := getBlkAddr(s2_req_paddr(i)) 430 toMSHRArbiter.io.in(i).bits.vSetIdx := s2_req_vSetIdx(i) 431 } 432 433 toMSHR <> toMSHRArbiter.io.out 434 435 s2_flush := io.flush 436 437 val s2_finish = (0 until PortNumber).map(i => has_send(i) || !s2_miss(i) || toMSHRArbiter.io.in(i).fire).reduce(_&&_) 438 s2_ready := s2_finish || !s2_valid 439 s2_fire := s2_valid && s2_finish && !s2_flush 440 441 /** PerfAccumulate */ 442 // the number of prefetch request received from ftq 443 XSPerfAccumulate("prefetch_req_receive", fromFtq.req.fire) 444 // the number of prefetch request sent to missUnit 445 XSPerfAccumulate("prefetch_req_send", toMSHR.fire) 446 XSPerfAccumulate("to_missUnit_stall", toMSHR.valid && !toMSHR.ready) 447 /** 448 * Count the number of requests that are filtered for various reasons. 449 * The number of prefetch discard in Performance Accumulator may be 450 * a littel larger the number of really discarded. Because there can 451 * be multiple reasons for a canceled request at the same time. 452 */ 453 // discard prefetch request by flush 454 // XSPerfAccumulate("fdip_prefetch_discard_by_tlb_except", p1_discard && p1_tlb_except) 455 // // discard prefetch request by hit icache SRAM 456 // XSPerfAccumulate("fdip_prefetch_discard_by_hit_cache", p2_discard && p1_meta_hit) 457 // // discard prefetch request by hit wirte SRAM 458 // XSPerfAccumulate("fdip_prefetch_discard_by_p1_monoitor", p1_discard && p1_monitor_hit) 459 // // discard prefetch request by pmp except or mmio 460 // XSPerfAccumulate("fdip_prefetch_discard_by_pmp", p2_discard && p2_pmp_except) 461 // // discard prefetch request by hit mainPipe info 462 // // XSPerfAccumulate("fdip_prefetch_discard_by_mainPipe", p2_discard && p2_mainPipe_hit) 463}