1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.fpu.FPU 26import xiangshan.backend.rob.RobLsqIO 27import xiangshan.cache._ 28import xiangshan.cache.mmu._ 29import xiangshan.frontend.FtqPtr 30import xiangshan.ExceptionNO._ 31import xiangshan.mem.mdp._ 32import xiangshan.backend.rob.RobPtr 33 34class LqPtr(implicit p: Parameters) extends CircularQueuePtr[LqPtr]( 35 p => p(XSCoreParamsKey).VirtualLoadQueueSize 36){ 37} 38 39object LqPtr { 40 def apply(f: Bool, v: UInt)(implicit p: Parameters): LqPtr = { 41 val ptr = Wire(new LqPtr) 42 ptr.flag := f 43 ptr.value := v 44 ptr 45 } 46} 47 48trait HasLoadHelper { this: XSModule => 49 def rdataHelper(uop: MicroOp, rdata: UInt): UInt = { 50 val fpWen = uop.ctrl.fpWen 51 LookupTree(uop.ctrl.fuOpType, List( 52 LSUOpType.lb -> SignExt(rdata(7, 0) , XLEN), 53 LSUOpType.lh -> SignExt(rdata(15, 0), XLEN), 54 /* 55 riscv-spec-20191213: 12.2 NaN Boxing of Narrower Values 56 Any operation that writes a narrower result to an f register must write 57 all 1s to the uppermost FLEN−n bits to yield a legal NaN-boxed value. 58 */ 59 LSUOpType.lw -> Mux(fpWen, FPU.box(rdata, FPU.S), SignExt(rdata(31, 0), XLEN)), 60 LSUOpType.ld -> Mux(fpWen, FPU.box(rdata, FPU.D), SignExt(rdata(63, 0), XLEN)), 61 LSUOpType.lbu -> ZeroExt(rdata(7, 0) , XLEN), 62 LSUOpType.lhu -> ZeroExt(rdata(15, 0), XLEN), 63 LSUOpType.lwu -> ZeroExt(rdata(31, 0), XLEN), 64 65 // hypervisor 66 LSUOpType.hlvb -> SignExt(rdata(7, 0), XLEN), 67 LSUOpType.hlvh -> SignExt(rdata(15, 0), XLEN), 68 LSUOpType.hlvw -> SignExt(rdata(31, 0), XLEN), 69 LSUOpType.hlvd -> SignExt(rdata(63, 0), XLEN), 70 LSUOpType.hlvbu -> ZeroExt(rdata(7, 0), XLEN), 71 LSUOpType.hlvhu -> ZeroExt(rdata(15, 0), XLEN), 72 LSUOpType.hlvwu -> ZeroExt(rdata(31, 0), XLEN), 73 LSUOpType.hlvxhu -> ZeroExt(rdata(15, 0), XLEN), 74 LSUOpType.hlvxwu -> ZeroExt(rdata(31, 0), XLEN), 75 )) 76 } 77} 78 79class LqEnqIO(implicit p: Parameters) extends XSBundle { 80 val canAccept = Output(Bool()) 81 val sqCanAccept = Input(Bool()) 82 val needAlloc = Vec(exuParameters.LsExuCnt, Input(Bool())) 83 val req = Vec(exuParameters.LsExuCnt, Flipped(ValidIO(new MicroOp))) 84 val resp = Vec(exuParameters.LsExuCnt, Output(new LqPtr)) 85} 86 87class LqTriggerIO(implicit p: Parameters) extends XSBundle { 88 val hitLoadAddrTriggerHitVec = Input(Vec(3, Bool())) 89 val lqLoadAddrTriggerHitVec = Output(Vec(3, Bool())) 90} 91 92class LoadQueueTopDownIO(implicit p: Parameters) extends XSBundle { 93 val robHeadVaddr = Flipped(Valid(UInt(VAddrBits.W))) 94 val robHeadTlbReplay = Output(Bool()) 95 val robHeadTlbMiss = Output(Bool()) 96 val robHeadLoadVio = Output(Bool()) 97 val robHeadLoadMSHR = Output(Bool()) 98 val robHeadMissInDTlb = Input(Bool()) 99 val robHeadOtherReplay = Output(Bool()) 100} 101 102class LoadQueue(implicit p: Parameters) extends XSModule 103 with HasDCacheParameters 104 with HasCircularQueuePtrHelper 105 with HasLoadHelper 106 with HasPerfEvents 107{ 108 val io = IO(new Bundle() { 109 val redirect = Flipped(Valid(new Redirect)) 110 val enq = new LqEnqIO 111 val ldu = new Bundle() { 112 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 113 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 114 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 115 } 116 val sta = new Bundle() { 117 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 118 } 119 val std = new Bundle() { 120 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new ExuOutput))) // from store_s0, store data, send to sq from rs 121 } 122 val sq = new Bundle() { 123 val stAddrReadySqPtr = Input(new SqPtr) 124 val stAddrReadyVec = Input(Vec(StoreQueueSize, Bool())) 125 val stDataReadySqPtr = Input(new SqPtr) 126 val stDataReadyVec = Input(Vec(StoreQueueSize, Bool())) 127 val stIssuePtr = Input(new SqPtr) 128 val sqEmpty = Input(Bool()) 129 } 130 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new ExuOutput)) 131 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 132 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 133 // val refill = Flipped(ValidIO(new Refill)) 134 val tl_d_channel = Input(new DcacheToLduForwardIO) 135 val release = Flipped(Valid(new Release)) 136 val nuke_rollback = Output(Valid(new Redirect)) 137 val nack_rollback = Output(Valid(new Redirect)) 138 val rob = Flipped(new RobLsqIO) 139 val uncache = new UncacheWordIO 140 val exceptionAddr = new ExceptionAddrIO 141 val lqFull = Output(Bool()) 142 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 143 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 144 val lq_rep_full = Output(Bool()) 145 val tlbReplayDelayCycleCtrl = Vec(4, Input(UInt(ReSelectLen.W))) 146 val l2_hint = Input(Valid(new L2ToL1Hint())) 147 val tlb_hint = Flipped(new TlbHintIO) 148 val lqEmpty = Output(Bool()) 149 val debugTopDown = new LoadQueueTopDownIO 150 }) 151 152 val loadQueueRAR = Module(new LoadQueueRAR) // read-after-read violation 153 val loadQueueRAW = Module(new LoadQueueRAW) // read-after-write violation 154 val loadQueueReplay = Module(new LoadQueueReplay) // enqueue if need replay 155 val virtualLoadQueue = Module(new VirtualLoadQueue) // control state 156 val exceptionBuffer = Module(new LqExceptionBuffer) // exception buffer 157 val uncacheBuffer = Module(new UncacheBuffer) // uncache buffer 158 /** 159 * LoadQueueRAR 160 */ 161 loadQueueRAR.io.redirect <> io.redirect 162 loadQueueRAR.io.release <> io.release 163 loadQueueRAR.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 164 for (w <- 0 until LoadPipelineWidth) { 165 loadQueueRAR.io.query(w).req <> io.ldu.ldld_nuke_query(w).req // from load_s1 166 loadQueueRAR.io.query(w).resp <> io.ldu.ldld_nuke_query(w).resp // to load_s2 167 loadQueueRAR.io.query(w).revoke := io.ldu.ldld_nuke_query(w).revoke // from load_s3 168 } 169 170 /** 171 * LoadQueueRAW 172 */ 173 loadQueueRAW.io.redirect <> io.redirect 174 loadQueueRAW.io.storeIn <> io.sta.storeAddrIn 175 loadQueueRAW.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 176 loadQueueRAW.io.stIssuePtr <> io.sq.stIssuePtr 177 for (w <- 0 until LoadPipelineWidth) { 178 loadQueueRAW.io.query(w).req <> io.ldu.stld_nuke_query(w).req // from load_s1 179 loadQueueRAW.io.query(w).resp <> io.ldu.stld_nuke_query(w).resp // to load_s2 180 loadQueueRAW.io.query(w).revoke := io.ldu.stld_nuke_query(w).revoke // from load_s3 181 } 182 183 /** 184 * VirtualLoadQueue 185 */ 186 virtualLoadQueue.io.redirect <> io.redirect 187 virtualLoadQueue.io.enq <> io.enq 188 virtualLoadQueue.io.ldin <> io.ldu.ldin // from load_s3 189 virtualLoadQueue.io.lqFull <> io.lqFull 190 virtualLoadQueue.io.lqDeq <> io.lqDeq 191 virtualLoadQueue.io.lqCancelCnt <> io.lqCancelCnt 192 virtualLoadQueue.io.lqEmpty <> io.lqEmpty 193 194 /** 195 * Load queue exception buffer 196 */ 197 exceptionBuffer.io.redirect <> io.redirect 198 for ((buff, w) <- exceptionBuffer.io.req.zipWithIndex) { 199 buff.valid := io.ldu.ldin(w).valid // from load_s3 200 buff.bits := io.ldu.ldin(w).bits 201 } 202 io.exceptionAddr <> exceptionBuffer.io.exceptionAddr 203 204 /** 205 * Load uncache buffer 206 */ 207 uncacheBuffer.io.redirect <> io.redirect 208 uncacheBuffer.io.ldout <> io.ldout 209 uncacheBuffer.io.ld_raw_data <> io.ld_raw_data 210 uncacheBuffer.io.rob <> io.rob 211 uncacheBuffer.io.uncache <> io.uncache 212 for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) { 213 buff.valid := io.ldu.ldin(w).valid // from load_s3 214 buff.bits := io.ldu.ldin(w).bits // from load_s3 215 } 216 217 218 io.nuke_rollback := loadQueueRAW.io.rollback 219 io.nack_rollback := uncacheBuffer.io.rollback 220 221 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 222 223 /** 224 * LoadQueueReplay 225 */ 226 loadQueueReplay.io.redirect <> io.redirect 227 loadQueueReplay.io.enq <> io.ldu.ldin // from load_s3 228 loadQueueReplay.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 229 loadQueueReplay.io.storeDataIn <> io.std.storeDataIn // from store_s0 230 loadQueueReplay.io.replay <> io.replay 231 //loadQueueReplay.io.refill <> io.refill 232 loadQueueReplay.io.tl_d_channel <> io.tl_d_channel 233 loadQueueReplay.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 234 loadQueueReplay.io.stAddrReadyVec <> io.sq.stAddrReadyVec 235 loadQueueReplay.io.stDataReadySqPtr <> io.sq.stDataReadySqPtr 236 loadQueueReplay.io.stDataReadyVec <> io.sq.stDataReadyVec 237 loadQueueReplay.io.sqEmpty <> io.sq.sqEmpty 238 loadQueueReplay.io.lqFull <> io.lq_rep_full 239 loadQueueReplay.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 240 loadQueueReplay.io.rarFull <> loadQueueRAR.io.lqFull 241 loadQueueReplay.io.rawFull <> loadQueueRAW.io.lqFull 242 loadQueueReplay.io.l2_hint <> io.l2_hint 243 loadQueueReplay.io.tlb_hint <> io.tlb_hint 244 loadQueueReplay.io.tlbReplayDelayCycleCtrl <> io.tlbReplayDelayCycleCtrl 245 246 loadQueueReplay.io.debugTopDown <> io.debugTopDown 247 248 val full_mask = Cat(loadQueueRAR.io.lqFull, loadQueueRAW.io.lqFull, loadQueueReplay.io.lqFull) 249 XSPerfAccumulate("full_mask_000", full_mask === 0.U) 250 XSPerfAccumulate("full_mask_001", full_mask === 1.U) 251 XSPerfAccumulate("full_mask_010", full_mask === 2.U) 252 XSPerfAccumulate("full_mask_011", full_mask === 3.U) 253 XSPerfAccumulate("full_mask_100", full_mask === 4.U) 254 XSPerfAccumulate("full_mask_101", full_mask === 5.U) 255 XSPerfAccumulate("full_mask_110", full_mask === 6.U) 256 XSPerfAccumulate("full_mask_111", full_mask === 7.U) 257 XSPerfAccumulate("nuke_rollback", io.nuke_rollback.valid) 258 XSPerfAccumulate("nack_rollabck", io.nack_rollback.valid) 259 260 // perf cnt 261 val perfEvents = Seq(virtualLoadQueue, loadQueueRAR, loadQueueRAW, loadQueueReplay).flatMap(_.getPerfEvents) ++ 262 Seq( 263 ("full_mask_000", full_mask === 0.U), 264 ("full_mask_001", full_mask === 1.U), 265 ("full_mask_010", full_mask === 2.U), 266 ("full_mask_011", full_mask === 3.U), 267 ("full_mask_100", full_mask === 4.U), 268 ("full_mask_101", full_mask === 5.U), 269 ("full_mask_110", full_mask === 6.U), 270 ("full_mask_111", full_mask === 7.U), 271 ("nuke_rollback", io.nuke_rollback.valid), 272 ("nack_rollback", io.nack_rollback.valid) 273 ) 274 generatePerfEvent() 275 // end 276}