xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala (revision 25a80bcea53d3f520075270aea9ffbe705ac5537) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan.mem.prefetch
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config.Parameters
22import utility.MemReqSource
23import xiangshan._
24import xiangshan.backend.fu.PMPRespBundle
25import xiangshan.cache.mmu.TlbRequestIO
26import xiangshan.mem.{LdPrefetchTrainBundle, StPrefetchTrainBundle, L1PrefetchReq}
27import xiangshan.backend._
28
29class L2PrefetchReq(implicit p: Parameters) extends XSBundle {
30  val addr = UInt(PAddrBits.W)
31  val source = UInt(MemReqSource.reqSourceBits.W)
32}
33
34class PrefetcherIO()(implicit p: Parameters) extends XSBundle {
35  val ld_in = Flipped(Vec(backendParams.LdExuCnt, ValidIO(new LdPrefetchTrainBundle())))
36  val st_in = Flipped(Vec(backendParams.StaExuCnt, ValidIO(new StPrefetchTrainBundle())))
37  val tlb_req = new TlbRequestIO(nRespDups = 2)
38  val pmp_resp = Flipped(new PMPRespBundle())
39  val l1_req = DecoupledIO(new L1PrefetchReq())
40  val l2_req = ValidIO(new L2PrefetchReq())
41  val l3_req = ValidIO(UInt(PAddrBits.W)) // TODO: l3 pf source
42  val enable = Input(Bool())
43}
44
45class PrefetchReqBundle()(implicit p: Parameters) extends XSBundle {
46  val vaddr       = UInt(VAddrBits.W)
47  val paddr       = UInt(PAddrBits.W)
48  val pc          = UInt(VAddrBits.W)
49  val miss        = Bool()
50  val pfHitStream = Bool()
51}
52
53trait PrefetcherParams
54
55abstract class BasePrefecher()(implicit p: Parameters) extends XSModule {
56  val io = IO(new PrefetcherIO())
57
58  io.l3_req.valid := false.B
59  io.l3_req.bits  := DontCare
60}