xref: /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala (revision 3136ee6a0600eb77c23effda5389fe3f858a813c) 
1package xiangshan.mem
2
3import chisel3._
4import chisel3.util._
5import utils.{XSDebug, XSInfo}
6import xiangshan._
7import xiangshan.cache.{DCacheLineIO, DCacheWordReq, MemoryOpConstants}
8
9// Fake Store buffer for XiangShan Out of Order LSU
10class FakeSbuffer extends XSModule {
11  val io = IO(new Bundle() {
12    val in = Vec(StorePipelineWidth, Flipped(Decoupled(new DCacheWordReq)))
13    val dcache = new DCacheLineIO
14    val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
15  })
16
17  assert(!(io.in(1).valid && !io.in(0).valid))
18
19  // assign default values to signals
20  io.in(1).ready := false.B
21
22  io.dcache.req.valid := false.B
23  io.dcache.req.bits := DontCare
24  io.dcache.resp.ready := false.B
25
26  val s_invalid :: s_req :: s_resp :: Nil = Enum(3)
27
28  val state = RegInit(s_invalid)
29
30  val req = Reg(new DCacheWordReq)
31
32  XSDebug("state: %d\n", state)
33
34  io.in(0).ready := state === s_invalid
35
36  def word_addr(addr: UInt) = (addr >> 3) << 3
37  def block_addr(addr: UInt) = (addr >> 6) << 6
38
39  // --------------------------------------------
40  // s_invalid: receive requests
41  when (state === s_invalid) {
42    when (io.in(0).fire()) {
43      req   := io.in(0).bits
44      state := s_req
45    }
46  }
47
48  val wdataVec = WireInit(VecInit(Seq.fill(8)(0.U(64.W))))
49  val wmaskVec = WireInit(VecInit(Seq.fill(8)(0.U(8.W))))
50  wdataVec(req.addr(5,3)) := req.data
51  wmaskVec(req.addr(5,3)) := req.mask
52
53  when (state === s_req) {
54    val dcache_req = io.dcache.req
55    dcache_req.valid := true.B
56    dcache_req.bits.cmd  := MemoryOpConstants.M_XWR
57    dcache_req.bits.addr := block_addr(req.addr)
58    dcache_req.bits.data := wdataVec.asUInt
59    dcache_req.bits.mask := wmaskVec.asUInt
60    dcache_req.bits.meta := DontCare
61
62    when (dcache_req.fire()) {
63      state := s_resp
64    }
65  }
66
67  when (state === s_resp) {
68    io.dcache.resp.ready := true.B
69    when (io.dcache.resp.fire()) {
70      state := s_invalid
71    }
72  }
73
74  // do forwarding here
75  for (i <- 0 until LoadPipelineWidth) {
76    val addr_match = word_addr(io.forward(i).paddr) === word_addr(req.addr)
77    val mask = io.forward(i).mask & req.mask(7, 0)
78    val mask_match = mask =/= 0.U
79    val need_forward = state =/= s_invalid && addr_match && mask_match
80
81    io.forward(i).forwardMask := Mux(need_forward, VecInit(mask.asBools),
82      VecInit(0.U(8.W).asBools))
83    io.forward(i).forwardData := VecInit((0 until 8) map {i => req.data((i + 1) * 8 - 1, i * 8)})
84  }
85
86  XSInfo(io.in(0).fire(), "ensbuffer addr 0x%x wdata 0x%x mask %b\n", io.in(0).bits.addr, io.in(0).bits.data, io.in(0).bits.mask)
87  XSInfo(io.in(1).fire(), "ensbuffer addr 0x%x wdata 0x%x mask %b\n", io.in(1).bits.addr, io.in(1).bits.data, io.in(0).bits.mask)
88  XSInfo(io.dcache.req.fire(), "desbuffer addr 0x%x wdata 0x%x mask %b\n", io.dcache.req.bits.addr, io.dcache.req.bits.data, io.dcache.req.bits.mask)
89}
90