1*730cfbc0SXuan Hupackage xiangshan.backend.issue 2*730cfbc0SXuan Hu 3*730cfbc0SXuan Huimport chipsalliance.rocketchip.config.Parameters 4*730cfbc0SXuan Huimport freechips.rocketchip.diplomacy.LazyModule 5*730cfbc0SXuan Huimport top.{ArgParser, BaseConfig, Generator} 6*730cfbc0SXuan Huimport xiangshan.{XSCoreParameters, XSCoreParamsKey} 7*730cfbc0SXuan Hu 8*730cfbc0SXuan Huobject IssueQueueMain extends App { 9*730cfbc0SXuan Hu override def main(args: Array[String]): Unit = { 10*730cfbc0SXuan Hu val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args) 11*730cfbc0SXuan Hu val backendParams = config(XSCoreParamsKey).backendParams 12*730cfbc0SXuan Hu 13*730cfbc0SXuan Hu val iqParams: IssueBlockParams = backendParams.intSchdParams.get.issueBlockParams.head 14*730cfbc0SXuan Hu val iq: IssueQueue = LazyModule(new IssueQueue(iqParams)(config.alterPartial({ case XSCoreParamsKey => XSCoreParameters() }))) 15*730cfbc0SXuan Hu 16*730cfbc0SXuan Hu Generator.execute( 17*730cfbc0SXuan Hu firrtlOpts, 18*730cfbc0SXuan Hu iq.module, 19*730cfbc0SXuan Hu firrtlComplier 20*730cfbc0SXuan Hu ) 21*730cfbc0SXuan Hu } 22*730cfbc0SXuan Hu 23*730cfbc0SXuan Hu} 24