1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #include <drivers/allwinner/axp.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park const uint8_t axp_chip_id = AXP805_CHIP_ID; 10*54fd6939SJiyong Park const char *const axp_compatible = "x-powers,axp805"; 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* 13*54fd6939SJiyong Park * The "dcdcd" split changes the step size by a factor of 5, not 2; 14*54fd6939SJiyong Park * disallow values above the split to maintain accuracy. 15*54fd6939SJiyong Park */ 16*54fd6939SJiyong Park const struct axp_regulator axp_regulators[] = { 17*54fd6939SJiyong Park {"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0}, 18*54fd6939SJiyong Park {"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1}, 19*54fd6939SJiyong Park {"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2}, 20*54fd6939SJiyong Park {"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3}, 21*54fd6939SJiyong Park {"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4}, 22*54fd6939SJiyong Park {"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5}, 23*54fd6939SJiyong Park {"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6}, 24*54fd6939SJiyong Park {"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7}, 25*54fd6939SJiyong Park {"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0}, 26*54fd6939SJiyong Park {"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1}, 27*54fd6939SJiyong Park {"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2}, 28*54fd6939SJiyong Park {"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3}, 29*54fd6939SJiyong Park {"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4}, 30*54fd6939SJiyong Park {"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5}, 31*54fd6939SJiyong Park {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6}, 32*54fd6939SJiyong Park {} 33*54fd6939SJiyong Park }; 34