1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park #ifndef IMX_UART_H 7*54fd6939SJiyong Park #define IMX_UART_H 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park #include <drivers/console.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park #define IMX_UART_RXD_OFFSET 0x00 12*54fd6939SJiyong Park #define IMX_UART_RXD_CHARRDY BIT(15) 13*54fd6939SJiyong Park #define IMX_UART_RXD_ERR BIT(14) 14*54fd6939SJiyong Park #define IMX_UART_RXD_OVERRUN BIT(13) 15*54fd6939SJiyong Park #define IMX_UART_RXD_FRMERR BIT(12) 16*54fd6939SJiyong Park #define IMX_UART_RXD_BRK BIT(11) 17*54fd6939SJiyong Park #define IMX_UART_RXD_PRERR BIT(10) 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park #define IMX_UART_TXD_OFFSET 0x40 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park #define IMX_UART_CR1_OFFSET 0x80 22*54fd6939SJiyong Park #define IMX_UART_CR1_ADEN BIT(15) 23*54fd6939SJiyong Park #define IMX_UART_CR1_ADBR BIT(14) 24*54fd6939SJiyong Park #define IMX_UART_CR1_TRDYEN BIT(13) 25*54fd6939SJiyong Park #define IMX_UART_CR1_IDEN BIT(12) 26*54fd6939SJiyong Park #define IMX_UART_CR1_RRDYEN BIT(9) 27*54fd6939SJiyong Park #define IMX_UART_CR1_RXDMAEN BIT(8) 28*54fd6939SJiyong Park #define IMX_UART_CR1_IREN BIT(7) 29*54fd6939SJiyong Park #define IMX_UART_CR1_TXMPTYEN BIT(6) 30*54fd6939SJiyong Park #define IMX_UART_CR1_RTSDEN BIT(5) 31*54fd6939SJiyong Park #define IMX_UART_CR1_SNDBRK BIT(4) 32*54fd6939SJiyong Park #define IMX_UART_CR1_TXDMAEN BIT(3) 33*54fd6939SJiyong Park #define IMX_UART_CR1_ATDMAEN BIT(2) 34*54fd6939SJiyong Park #define IMX_UART_CR1_DOZE BIT(1) 35*54fd6939SJiyong Park #define IMX_UART_CR1_UARTEN BIT(0) 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park #define IMX_UART_CR2_OFFSET 0x84 38*54fd6939SJiyong Park #define IMX_UART_CR2_ESCI BIT(15) 39*54fd6939SJiyong Park #define IMX_UART_CR2_IRTS BIT(14) 40*54fd6939SJiyong Park #define IMX_UART_CR2_CTSC BIT(13) 41*54fd6939SJiyong Park #define IMX_UART_CR2_CTS BIT(12) 42*54fd6939SJiyong Park #define IMX_UART_CR2_ESCEN BIT(11) 43*54fd6939SJiyong Park #define IMX_UART_CR2_PREN BIT(8) 44*54fd6939SJiyong Park #define IMX_UART_CR2_PROE BIT(7) 45*54fd6939SJiyong Park #define IMX_UART_CR2_STPB BIT(6) 46*54fd6939SJiyong Park #define IMX_UART_CR2_WS BIT(5) 47*54fd6939SJiyong Park #define IMX_UART_CR2_RTSEN BIT(4) 48*54fd6939SJiyong Park #define IMX_UART_CR2_ATEN BIT(3) 49*54fd6939SJiyong Park #define IMX_UART_CR2_TXEN BIT(2) 50*54fd6939SJiyong Park #define IMX_UART_CR2_RXEN BIT(1) 51*54fd6939SJiyong Park #define IMX_UART_CR2_SRST BIT(0) 52*54fd6939SJiyong Park 53*54fd6939SJiyong Park #define IMX_UART_CR3_OFFSET 0x88 54*54fd6939SJiyong Park #define IMX_UART_CR3_DTREN BIT(13) 55*54fd6939SJiyong Park #define IMX_UART_CR3_PARERREN BIT(12) 56*54fd6939SJiyong Park #define IMX_UART_CR3_FARERREN BIT(11) 57*54fd6939SJiyong Park #define IMX_UART_CR3_DSD BIT(10) 58*54fd6939SJiyong Park #define IMX_UART_CR3_DCD BIT(9) 59*54fd6939SJiyong Park #define IMX_UART_CR3_RI BIT(8) 60*54fd6939SJiyong Park #define IMX_UART_CR3_ADNIMP BIT(7) 61*54fd6939SJiyong Park #define IMX_UART_CR3_RXDSEN BIT(6) 62*54fd6939SJiyong Park #define IMX_UART_CR3_AIRINTEN BIT(5) 63*54fd6939SJiyong Park #define IMX_UART_CR3_AWAKEN BIT(4) 64*54fd6939SJiyong Park #define IMX_UART_CR3_DTRDEN BIT(3) 65*54fd6939SJiyong Park #define IMX_UART_CR3_RXDMUXSEL BIT(2) 66*54fd6939SJiyong Park #define IMX_UART_CR3_INVT BIT(1) 67*54fd6939SJiyong Park #define IMX_UART_CR3_ACIEN BIT(0) 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park #define IMX_UART_CR4_OFFSET 0x8c 70*54fd6939SJiyong Park #define IMX_UART_CR4_INVR BIT(9) 71*54fd6939SJiyong Park #define IMX_UART_CR4_ENIRI BIT(8) 72*54fd6939SJiyong Park #define IMX_UART_CR4_WKEN BIT(7) 73*54fd6939SJiyong Park #define IMX_UART_CR4_IDDMAEN BIT(6) 74*54fd6939SJiyong Park #define IMX_UART_CR4_IRSC BIT(5) 75*54fd6939SJiyong Park #define IMX_UART_CR4_LPBYP BIT(4) 76*54fd6939SJiyong Park #define IMX_UART_CR4_TCEN BIT(3) 77*54fd6939SJiyong Park #define IMX_UART_CR4_BKEN BIT(2) 78*54fd6939SJiyong Park #define IMX_UART_CR4_OREN BIT(1) 79*54fd6939SJiyong Park #define IMX_UART_CR4_DREN BIT(0) 80*54fd6939SJiyong Park 81*54fd6939SJiyong Park #define IMX_UART_FCR_OFFSET 0x90 82*54fd6939SJiyong Park #define IMX_UART_FCR_TXTL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12) |\ 83*54fd6939SJiyong Park BIT(11) | BIT(10)) 84*54fd6939SJiyong Park #define IMX_UART_FCR_TXTL(x) ((x) << 10) 85*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV_MASK (BIT(9) | BIT(8) | BIT(7)) 86*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV7 (BIT(9) | BIT(8)) 87*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV1 (BIT(9) | BIT(7)) 88*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV2 BIT(9) 89*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV3 (BIT(8) | BIT(7)) 90*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV4 BIT(8) 91*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV5 BIT(7) 92*54fd6939SJiyong Park #define IMX_UART_FCR_RFDIV6 0 93*54fd6939SJiyong Park #define IMX_UART_FCR_DCEDTE BIT(6) 94*54fd6939SJiyong Park #define IMX_UART_FCR_RXTL_MASK (BIT(5) | BIT(4) | BIT(3) | BIT(2) |\ 95*54fd6939SJiyong Park BIT(1) | BIT(0)) 96*54fd6939SJiyong Park #define IMX_UART_FCR_RXTL(x) x 97*54fd6939SJiyong Park 98*54fd6939SJiyong Park #define IMX_UART_STAT1_OFFSET 0x94 99*54fd6939SJiyong Park #define IMX_UART_STAT1_PARITYERR BIT(15) 100*54fd6939SJiyong Park #define IMX_UART_STAT1_RTSS BIT(14) 101*54fd6939SJiyong Park #define IMX_UART_STAT1_TRDY BIT(13) 102*54fd6939SJiyong Park #define IMX_UART_STAT1_RTSD BIT(12) 103*54fd6939SJiyong Park #define IMX_UART_STAT1_ESCF BIT(11) 104*54fd6939SJiyong Park #define IMX_UART_STAT1_FRAMEERR BIT(10) 105*54fd6939SJiyong Park #define IMX_UART_STAT1_RRDY BIT(9) 106*54fd6939SJiyong Park #define IMX_UART_STAT1_AGTIM BIT(8) 107*54fd6939SJiyong Park #define IMX_UART_STAT1_DTRD BIT(7) 108*54fd6939SJiyong Park #define IMX_UART_STAT1_RXDS BIT(6) 109*54fd6939SJiyong Park #define IMX_UART_STAT1_AIRINT BIT(5) 110*54fd6939SJiyong Park #define IMX_UART_STAT1_AWAKE BIT(4) 111*54fd6939SJiyong Park #define IMX_UART_STAT1_SAD BIT(3) 112*54fd6939SJiyong Park 113*54fd6939SJiyong Park #define IMX_UART_STAT2_OFFSET 0x98 114*54fd6939SJiyong Park #define IMX_UART_STAT2_ADET BIT(15) 115*54fd6939SJiyong Park #define IMX_UART_STAT2_TXFE BIT(14) 116*54fd6939SJiyong Park #define IMX_UART_STAT2_DTRF BIT(13) 117*54fd6939SJiyong Park #define IMX_UART_STAT2_IDLE BIT(12) 118*54fd6939SJiyong Park #define IMX_UART_STAT2_ACST BIT(11) 119*54fd6939SJiyong Park #define IMX_UART_STAT2_RIDELT BIT(10) 120*54fd6939SJiyong Park #define IMX_UART_STAT2_RIIN BIT(9) 121*54fd6939SJiyong Park #define IMX_UART_STAT2_IRINT BIT(8) 122*54fd6939SJiyong Park #define IMX_UART_STAT2_WAKE BIT(7) 123*54fd6939SJiyong Park #define IMX_UART_STAT2_DCDDELT BIT(6) 124*54fd6939SJiyong Park #define IMX_UART_STAT2_DCDIN BIT(5) 125*54fd6939SJiyong Park #define IMX_UART_STAT2_RTSF BIT(4) 126*54fd6939SJiyong Park #define IMX_UART_STAT2_TXDC BIT(3) 127*54fd6939SJiyong Park #define IMX_UART_STAT2_BRCD BIT(2) 128*54fd6939SJiyong Park #define IMX_UART_STAT2_ORE BIT(1) 129*54fd6939SJiyong Park #define IMX_UART_STAT2_RCR BIT(0) 130*54fd6939SJiyong Park 131*54fd6939SJiyong Park #define IMX_UART_ESC_OFFSET 0x9c 132*54fd6939SJiyong Park 133*54fd6939SJiyong Park #define IMX_UART_TIM_OFFSET 0xa0 134*54fd6939SJiyong Park 135*54fd6939SJiyong Park #define IMX_UART_BIR_OFFSET 0xa4 136*54fd6939SJiyong Park 137*54fd6939SJiyong Park #define IMX_UART_BMR_OFFSET 0xa8 138*54fd6939SJiyong Park 139*54fd6939SJiyong Park #define IMX_UART_BRC_OFFSET 0xac 140*54fd6939SJiyong Park 141*54fd6939SJiyong Park #define IMX_UART_ONEMS_OFFSET 0xb0 142*54fd6939SJiyong Park 143*54fd6939SJiyong Park #define IMX_UART_TS_OFFSET 0xb4 144*54fd6939SJiyong Park #define IMX_UART_TS_FRCPERR BIT(13) 145*54fd6939SJiyong Park #define IMX_UART_TS_LOOP BIT(12) 146*54fd6939SJiyong Park #define IMX_UART_TS_DBGEN BIT(11) 147*54fd6939SJiyong Park #define IMX_UART_TS_LOOPIR BIT(10) 148*54fd6939SJiyong Park #define IMX_UART_TS_RXDBG BIT(9) 149*54fd6939SJiyong Park #define IMX_UART_TS_TXEMPTY BIT(6) 150*54fd6939SJiyong Park #define IMX_UART_TS_RXEMPTY BIT(5) 151*54fd6939SJiyong Park #define IMX_UART_TS_TXFULL BIT(4) 152*54fd6939SJiyong Park #define IMX_UART_TS_RXFULL BIT(3) 153*54fd6939SJiyong Park #define IMX_UART_TS_SOFTRST BIT(0) 154*54fd6939SJiyong Park 155*54fd6939SJiyong Park #ifndef __ASSEMBLER__ 156*54fd6939SJiyong Park 157*54fd6939SJiyong Park int console_imx_uart_register(uintptr_t baseaddr, 158*54fd6939SJiyong Park uint32_t clock, 159*54fd6939SJiyong Park uint32_t baud, 160*54fd6939SJiyong Park console_t *console); 161*54fd6939SJiyong Park #endif /*__ASSEMBLER__*/ 162*54fd6939SJiyong Park 163*54fd6939SJiyong Park #endif /* IMX_UART_H */ 164