1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright 2021 NXP 3*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 4*54fd6939SJiyong Park * 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef _INPUT_H_ 8*54fd6939SJiyong Park #define _INPUT_H_ 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park enum dram_types { 11*54fd6939SJiyong Park DDR4, 12*54fd6939SJiyong Park DDR3, 13*54fd6939SJiyong Park LPDDR4, 14*54fd6939SJiyong Park LPDDR3, 15*54fd6939SJiyong Park LPDDR2, 16*54fd6939SJiyong Park DDR5, 17*54fd6939SJiyong Park }; 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park enum dimm_types { 20*54fd6939SJiyong Park UDIMM, 21*54fd6939SJiyong Park SODIMM, 22*54fd6939SJiyong Park RDIMM, 23*54fd6939SJiyong Park LRDIMM, 24*54fd6939SJiyong Park NODIMM, 25*54fd6939SJiyong Park }; 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park struct input_basic { 28*54fd6939SJiyong Park enum dram_types dram_type; 29*54fd6939SJiyong Park enum dimm_types dimm_type; 30*54fd6939SJiyong Park int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4 31*54fd6939SJiyong Park */ 32*54fd6939SJiyong Park /* not used for protocols other than lpddr4 */ 33*54fd6939SJiyong Park int num_dbyte; /* number of dbytes physically instantiated */ 34*54fd6939SJiyong Park int num_active_dbyte_dfi0; /* number of active dbytes to be 35*54fd6939SJiyong Park * controlled by dfi0 36*54fd6939SJiyong Park */ 37*54fd6939SJiyong Park int num_active_dbyte_dfi1; /* number of active dbytes to be 38*54fd6939SJiyong Park * controlled by dfi1. Not used for 39*54fd6939SJiyong Park * protocols other than lpddr3 and 40*54fd6939SJiyong Park * lpddr4 41*54fd6939SJiyong Park */ 42*54fd6939SJiyong Park int num_anib; /* number of anibs physically instantiated */ 43*54fd6939SJiyong Park int num_rank_dfi0; /* number of ranks in dfi0 channel */ 44*54fd6939SJiyong Park int num_rank_dfi1; /* number of ranks in dfi1 channel */ 45*54fd6939SJiyong Park int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram 46*54fd6939SJiyong Park * type 47*54fd6939SJiyong Park */ 48*54fd6939SJiyong Park int num_pstates; 49*54fd6939SJiyong Park int frequency; /* memclk frequency in mhz -- round up */ 50*54fd6939SJiyong Park int pll_bypass; /* pll bypass enable */ 51*54fd6939SJiyong Park int dfi_freq_ratio; /* selected dfi frequency ratio */ 52*54fd6939SJiyong Park int dfi1exists; /* whether they phy config has dfi1 channel */ 53*54fd6939SJiyong Park int train2d; 54*54fd6939SJiyong Park int hard_macro_ver; 55*54fd6939SJiyong Park int read_dbienable; 56*54fd6939SJiyong Park int dfi_mode; /* no longer used */ 57*54fd6939SJiyong Park }; 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park struct input_advanced { 60*54fd6939SJiyong Park int d4rx_preamble_length; 61*54fd6939SJiyong Park int d4tx_preamble_length; 62*54fd6939SJiyong Park int ext_cal_res_val; /* external pull-down resistor */ 63*54fd6939SJiyong Park int is2ttiming; 64*54fd6939SJiyong Park int odtimpedance; 65*54fd6939SJiyong Park int tx_impedance; 66*54fd6939SJiyong Park int atx_impedance; 67*54fd6939SJiyong Park int mem_alert_en; 68*54fd6939SJiyong Park int mem_alert_puimp; 69*54fd6939SJiyong Park int mem_alert_vref_level; 70*54fd6939SJiyong Park int mem_alert_sync_bypass; 71*54fd6939SJiyong Park int dis_dyn_adr_tri; 72*54fd6939SJiyong Park int phy_mstr_train_interval; 73*54fd6939SJiyong Park int phy_mstr_max_req_to_ack; 74*54fd6939SJiyong Park int wdqsext; 75*54fd6939SJiyong Park int cal_interval; 76*54fd6939SJiyong Park int cal_once; 77*54fd6939SJiyong Park int dram_byte_swap; 78*54fd6939SJiyong Park int rx_en_back_off; 79*54fd6939SJiyong Park int train_sequence_ctrl; 80*54fd6939SJiyong Park int phy_gen2_umctl_opt; 81*54fd6939SJiyong Park int phy_gen2_umctl_f0rc5x; 82*54fd6939SJiyong Park int tx_slew_rise_dq; 83*54fd6939SJiyong Park int tx_slew_fall_dq; 84*54fd6939SJiyong Park int tx_slew_rise_ac; 85*54fd6939SJiyong Park int tx_slew_fall_ac; 86*54fd6939SJiyong Park int enable_high_clk_skew_fix; 87*54fd6939SJiyong Park int disable_unused_addr_lns; 88*54fd6939SJiyong Park int phy_init_sequence_num; 89*54fd6939SJiyong Park int cs_mode; /* rdimm */ 90*54fd6939SJiyong Park int cast_cs_to_cid; /* rdimm */ 91*54fd6939SJiyong Park }; 92*54fd6939SJiyong Park 93*54fd6939SJiyong Park struct input { 94*54fd6939SJiyong Park struct input_basic basic; 95*54fd6939SJiyong Park struct input_advanced adv; 96*54fd6939SJiyong Park unsigned int mr[7]; 97*54fd6939SJiyong Park unsigned int cs_d0; 98*54fd6939SJiyong Park unsigned int cs_d1; 99*54fd6939SJiyong Park unsigned int mirror; 100*54fd6939SJiyong Park unsigned int odt[4]; 101*54fd6939SJiyong Park unsigned int rcw[16]; 102*54fd6939SJiyong Park unsigned int rcw3x; 103*54fd6939SJiyong Park unsigned int vref; 104*54fd6939SJiyong Park }; 105*54fd6939SJiyong Park 106*54fd6939SJiyong Park #endif 107