1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright 2021 NXP
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park *
6*54fd6939SJiyong Park */
7*54fd6939SJiyong Park
8*54fd6939SJiyong Park #include <drivers/arm/gicv3.h>
9*54fd6939SJiyong Park #include <plat_gic.h>
10*54fd6939SJiyong Park #include <plat/common/platform.h>
11*54fd6939SJiyong Park
12*54fd6939SJiyong Park /*
13*54fd6939SJiyong Park * NXP common helper to initialize the GICv3 only driver.
14*54fd6939SJiyong Park */
plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr,uintptr_t nxp_gicr_addr,uint8_t plat_core_count,interrupt_prop_t * ls_interrupt_props,uint8_t ls_interrupt_prop_count,uintptr_t * target_mask_array,mpidr_hash_fn mpidr_to_core_pos)15*54fd6939SJiyong Park void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr,
16*54fd6939SJiyong Park uintptr_t nxp_gicr_addr,
17*54fd6939SJiyong Park uint8_t plat_core_count,
18*54fd6939SJiyong Park interrupt_prop_t *ls_interrupt_props,
19*54fd6939SJiyong Park uint8_t ls_interrupt_prop_count,
20*54fd6939SJiyong Park uintptr_t *target_mask_array,
21*54fd6939SJiyong Park mpidr_hash_fn mpidr_to_core_pos)
22*54fd6939SJiyong Park {
23*54fd6939SJiyong Park static struct gicv3_driver_data ls_gic_data;
24*54fd6939SJiyong Park
25*54fd6939SJiyong Park ls_gic_data.gicd_base = nxp_gicd_addr;
26*54fd6939SJiyong Park ls_gic_data.gicr_base = nxp_gicr_addr;
27*54fd6939SJiyong Park ls_gic_data.interrupt_props = ls_interrupt_props;
28*54fd6939SJiyong Park ls_gic_data.interrupt_props_num = ls_interrupt_prop_count;
29*54fd6939SJiyong Park ls_gic_data.rdistif_num = plat_core_count;
30*54fd6939SJiyong Park ls_gic_data.rdistif_base_addrs = target_mask_array;
31*54fd6939SJiyong Park ls_gic_data.mpidr_to_core_pos = mpidr_to_core_pos;
32*54fd6939SJiyong Park
33*54fd6939SJiyong Park gicv3_driver_init(&ls_gic_data);
34*54fd6939SJiyong Park }
35*54fd6939SJiyong Park
plat_ls_gic_init(void)36*54fd6939SJiyong Park void plat_ls_gic_init(void)
37*54fd6939SJiyong Park {
38*54fd6939SJiyong Park gicv3_distif_init();
39*54fd6939SJiyong Park gicv3_rdistif_init(plat_my_core_pos());
40*54fd6939SJiyong Park gicv3_cpuif_enable(plat_my_core_pos());
41*54fd6939SJiyong Park }
42*54fd6939SJiyong Park
43*54fd6939SJiyong Park /*
44*54fd6939SJiyong Park * NXP common helper to enable the GICv3 CPU interface
45*54fd6939SJiyong Park */
plat_ls_gic_cpuif_enable(void)46*54fd6939SJiyong Park void plat_ls_gic_cpuif_enable(void)
47*54fd6939SJiyong Park {
48*54fd6939SJiyong Park gicv3_cpuif_enable(plat_my_core_pos());
49*54fd6939SJiyong Park }
50*54fd6939SJiyong Park
51*54fd6939SJiyong Park /*
52*54fd6939SJiyong Park * NXP common helper to disable the GICv3 CPU interface
53*54fd6939SJiyong Park */
plat_ls_gic_cpuif_disable(void)54*54fd6939SJiyong Park void plat_ls_gic_cpuif_disable(void)
55*54fd6939SJiyong Park {
56*54fd6939SJiyong Park gicv3_cpuif_disable(plat_my_core_pos());
57*54fd6939SJiyong Park }
58*54fd6939SJiyong Park
59*54fd6939SJiyong Park /*
60*54fd6939SJiyong Park * NXP common helper to initialize the per cpu distributor interface in GICv3
61*54fd6939SJiyong Park */
plat_gic_pcpu_init(void)62*54fd6939SJiyong Park void plat_gic_pcpu_init(void)
63*54fd6939SJiyong Park {
64*54fd6939SJiyong Park gicv3_rdistif_init(plat_my_core_pos());
65*54fd6939SJiyong Park gicv3_cpuif_enable(plat_my_core_pos());
66*54fd6939SJiyong Park }
67*54fd6939SJiyong Park
68*54fd6939SJiyong Park /*
69*54fd6939SJiyong Park * Stubs for Redistributor power management. Although GICv3 doesn't have
70*54fd6939SJiyong Park * Redistributor interface, these are provided for the sake of uniform GIC API
71*54fd6939SJiyong Park */
plat_ls_gic_redistif_on(void)72*54fd6939SJiyong Park void plat_ls_gic_redistif_on(void)
73*54fd6939SJiyong Park {
74*54fd6939SJiyong Park }
75*54fd6939SJiyong Park
plat_ls_gic_redistif_off(void)76*54fd6939SJiyong Park void plat_ls_gic_redistif_off(void)
77*54fd6939SJiyong Park {
78*54fd6939SJiyong Park }
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