1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright 2021 NXP 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park * 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park #include <assert.h> 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <common/debug.h> 11*54fd6939SJiyong Park #include <lib/mmio.h> 12*54fd6939SJiyong Park #include <lib/xlat_tables/xlat_tables_v2.h> 13*54fd6939SJiyong Park #include <qspi.h> 14*54fd6939SJiyong Park qspi_io_setup(uintptr_t nxp_qspi_flash_addr,size_t nxp_qspi_flash_size,uintptr_t fip_offset)15*54fd6939SJiyong Parkint qspi_io_setup(uintptr_t nxp_qspi_flash_addr, 16*54fd6939SJiyong Park size_t nxp_qspi_flash_size, 17*54fd6939SJiyong Park uintptr_t fip_offset) 18*54fd6939SJiyong Park { 19*54fd6939SJiyong Park uint32_t qspi_mcr_val = qspi_in32(CHS_QSPI_MCR); 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park /* Enable and change endianness of QSPI IP */ 22*54fd6939SJiyong Park qspi_out32(CHS_QSPI_MCR, (qspi_mcr_val | CHS_QSPI_64LE)); 23*54fd6939SJiyong Park 24*54fd6939SJiyong Park /* Adding QSPI Memory Map in XLAT Table */ 25*54fd6939SJiyong Park mmap_add_region(nxp_qspi_flash_addr, nxp_qspi_flash_addr, 26*54fd6939SJiyong Park nxp_qspi_flash_size, MT_MEMORY | MT_RW); 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park return 0; 29*54fd6939SJiyong Park } 30