1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef PWRC_H 8*54fd6939SJiyong Park #define PWRC_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #define PPOFFR_OFF 0x0 11*54fd6939SJiyong Park #define PPONR_OFF 0x4 12*54fd6939SJiyong Park #define PCOFFR_OFF 0x8 13*54fd6939SJiyong Park #define PWKUPR_OFF 0xc 14*54fd6939SJiyong Park #define PSYSR_OFF 0x10 15*54fd6939SJiyong Park 16*54fd6939SJiyong Park #define PWKUPR_WEN (1ull << 31) 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park #define PSYSR_AFF_L2 (1U << 31) 19*54fd6939SJiyong Park #define PSYSR_AFF_L1 (1 << 30) 20*54fd6939SJiyong Park #define PSYSR_AFF_L0 (1 << 29) 21*54fd6939SJiyong Park #define PSYSR_WEN (1 << 28) 22*54fd6939SJiyong Park #define PSYSR_PC (1 << 27) 23*54fd6939SJiyong Park #define PSYSR_PP (1 << 26) 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park #define PSYSR_WK_SHIFT (24) 26*54fd6939SJiyong Park #define PSYSR_WK_MASK (0x3) 27*54fd6939SJiyong Park #define PSYSR_WK(x) (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK) 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park #define WKUP_COLD 0x0 30*54fd6939SJiyong Park #define WKUP_RESET 0x1 31*54fd6939SJiyong Park #define WKUP_PPONR 0x2 32*54fd6939SJiyong Park #define WKUP_GICREQ 0x3 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park #define RCAR_INVALID (0xffffffffU) 35*54fd6939SJiyong Park #define PSYSR_INVALID 0xffffffff 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park #define RCAR_CLUSTER_A53A57 (0U) 38*54fd6939SJiyong Park #define RCAR_CLUSTER_CA53 (1U) 39*54fd6939SJiyong Park #define RCAR_CLUSTER_CA57 (2U) 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park #ifndef __ASSEMBLER__ 42*54fd6939SJiyong Park void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr); 43*54fd6939SJiyong Park void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr); 44*54fd6939SJiyong Park void rcar_pwrc_clusteroff(uint64_t mpidr); 45*54fd6939SJiyong Park void rcar_pwrc_cpuoff(uint64_t mpidr); 46*54fd6939SJiyong Park void rcar_pwrc_cpuon(uint64_t mpidr); 47*54fd6939SJiyong Park int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr); 48*54fd6939SJiyong Park void rcar_pwrc_setup(void); 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr); 51*54fd6939SJiyong Park uint32_t rcar_pwrc_status(uint64_t mpidr); 52*54fd6939SJiyong Park uint32_t rcar_pwrc_get_cluster(void); 53*54fd6939SJiyong Park uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr); 54*54fd6939SJiyong Park uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type); 55*54fd6939SJiyong Park void rcar_pwrc_restore_timer_state(void); 56*54fd6939SJiyong Park void plat_secondary_reset(void); 57*54fd6939SJiyong Park 58*54fd6939SJiyong Park void rcar_pwrc_code_copy_to_system_ram(void); 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park #if !PMIC_ROHM_BD9571 61*54fd6939SJiyong Park void rcar_pwrc_system_reset(void); 62*54fd6939SJiyong Park #endif 63*54fd6939SJiyong Park 64*54fd6939SJiyong Park #if RCAR_SYSTEM_SUSPEND 65*54fd6939SJiyong Park void rcar_pwrc_go_suspend_to_ram(void); 66*54fd6939SJiyong Park void rcar_pwrc_set_suspend_to_ram(void); 67*54fd6939SJiyong Park void rcar_pwrc_init_suspend_to_ram(void); 68*54fd6939SJiyong Park void rcar_pwrc_suspend_to_ram(void); 69*54fd6939SJiyong Park #endif 70*54fd6939SJiyong Park 71*54fd6939SJiyong Park extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack, 72*54fd6939SJiyong Park void *arg); 73*54fd6939SJiyong Park #endif 74*54fd6939SJiyong Park 75*54fd6939SJiyong Park #endif /* PWRC_H */ 76