1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef PL011_H 8*54fd6939SJiyong Park #define PL011_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <drivers/console.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* PL011 Registers */ 13*54fd6939SJiyong Park #define UARTDR 0x000 14*54fd6939SJiyong Park #define UARTRSR 0x004 15*54fd6939SJiyong Park #define UARTECR 0x004 16*54fd6939SJiyong Park #define UARTFR 0x018 17*54fd6939SJiyong Park #define UARTIMSC 0x038 18*54fd6939SJiyong Park #define UARTRIS 0x03C 19*54fd6939SJiyong Park #define UARTICR 0x044 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park /* PL011 registers (out of the SBSA specification) */ 22*54fd6939SJiyong Park #if !PL011_GENERIC_UART 23*54fd6939SJiyong Park #define UARTILPR 0x020 24*54fd6939SJiyong Park #define UARTIBRD 0x024 25*54fd6939SJiyong Park #define UARTFBRD 0x028 26*54fd6939SJiyong Park #define UARTLCR_H 0x02C 27*54fd6939SJiyong Park #define UARTCR 0x030 28*54fd6939SJiyong Park #define UARTIFLS 0x034 29*54fd6939SJiyong Park #define UARTMIS 0x040 30*54fd6939SJiyong Park #define UARTDMACR 0x048 31*54fd6939SJiyong Park #endif /* !PL011_GENERIC_UART */ 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park /* Data status bits */ 34*54fd6939SJiyong Park #define UART_DATA_ERROR_MASK 0x0F00 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park /* Status reg bits */ 37*54fd6939SJiyong Park #define UART_STATUS_ERROR_MASK 0x0F 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park /* Flag reg bits */ 40*54fd6939SJiyong Park #define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ 41*54fd6939SJiyong Park #define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ 42*54fd6939SJiyong Park #define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ 43*54fd6939SJiyong Park #define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ 44*54fd6939SJiyong Park #define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ 45*54fd6939SJiyong Park #define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ 46*54fd6939SJiyong Park #define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ 47*54fd6939SJiyong Park #define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ 48*54fd6939SJiyong Park #define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park #define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ 51*54fd6939SJiyong Park #define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ 52*54fd6939SJiyong Park #define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */ 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park /* Control reg bits */ 55*54fd6939SJiyong Park #if !PL011_GENERIC_UART 56*54fd6939SJiyong Park #define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ 57*54fd6939SJiyong Park #define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ 58*54fd6939SJiyong Park #define PL011_UARTCR_RTS (1 << 11) /* Request to send */ 59*54fd6939SJiyong Park #define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ 60*54fd6939SJiyong Park #define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ 61*54fd6939SJiyong Park #define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ 62*54fd6939SJiyong Park #define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ 63*54fd6939SJiyong Park #define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ 64*54fd6939SJiyong Park 65*54fd6939SJiyong Park #if !defined(PL011_LINE_CONTROL) 66*54fd6939SJiyong Park /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ 67*54fd6939SJiyong Park #define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) 68*54fd6939SJiyong Park #endif 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park /* Line Control Register Bits */ 71*54fd6939SJiyong Park #define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ 72*54fd6939SJiyong Park #define PL011_UARTLCR_H_WLEN_8 (3 << 5) 73*54fd6939SJiyong Park #define PL011_UARTLCR_H_WLEN_7 (2 << 5) 74*54fd6939SJiyong Park #define PL011_UARTLCR_H_WLEN_6 (1 << 5) 75*54fd6939SJiyong Park #define PL011_UARTLCR_H_WLEN_5 (0 << 5) 76*54fd6939SJiyong Park #define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ 77*54fd6939SJiyong Park #define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ 78*54fd6939SJiyong Park #define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ 79*54fd6939SJiyong Park #define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ 80*54fd6939SJiyong Park #define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park #endif /* !PL011_GENERIC_UART */ 83*54fd6939SJiyong Park 84*54fd6939SJiyong Park #ifndef __ASSEMBLER__ 85*54fd6939SJiyong Park 86*54fd6939SJiyong Park #include <stdint.h> 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park /* 89*54fd6939SJiyong Park * Initialize a new PL011 console instance and register it with the console 90*54fd6939SJiyong Park * framework. The |console| pointer must point to storage that will be valid 91*54fd6939SJiyong Park * for the lifetime of the console, such as a global or static local variable. 92*54fd6939SJiyong Park * Its contents will be reinitialized from scratch. 93*54fd6939SJiyong Park */ 94*54fd6939SJiyong Park int console_pl011_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, 95*54fd6939SJiyong Park console_t *console); 96*54fd6939SJiyong Park 97*54fd6939SJiyong Park #endif /*__ASSEMBLER__*/ 98*54fd6939SJiyong Park 99*54fd6939SJiyong Park #endif /* PL011_H */ 100