1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015 - 2020, Broadcom 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef DMU_H 8*54fd6939SJiyong Park #define DMU_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park /* Clock field should be 2 bits only */ 11*54fd6939SJiyong Park #define CLKCONFIG_MASK 0x3 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park /* argument */ 14*54fd6939SJiyong Park struct DmuBlockEnable { 15*54fd6939SJiyong Park uint32_t sotp:1; 16*54fd6939SJiyong Park uint32_t pka_rng:1; 17*54fd6939SJiyong Park uint32_t crypto:1; 18*54fd6939SJiyong Park uint32_t spl:1; 19*54fd6939SJiyong Park uint32_t cdru_vgm:1; 20*54fd6939SJiyong Park uint32_t apbs_s0_idm:1; 21*54fd6939SJiyong Park uint32_t smau_s0_idm:1; 22*54fd6939SJiyong Park }; 23*54fd6939SJiyong Park 24*54fd6939SJiyong Park /* prototype */ 25*54fd6939SJiyong Park uint32_t bcm_dmu_block_enable(struct DmuBlockEnable dbe); 26*54fd6939SJiyong Park uint32_t bcm_dmu_block_disable(struct DmuBlockEnable dbe); 27*54fd6939SJiyong Park uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel); 28*54fd6939SJiyong Park uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num); 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park #define PLL_FREQ_BYPASS 0x0 31*54fd6939SJiyong Park #define PLL_FREQ_FULL 0x1 32*54fd6939SJiyong Park #define PLL_FREQ_HALF 0x2 33*54fd6939SJiyong Park #define PLL_FREQ_QRTR 0x3 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park #endif 36