1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright 2020-2021 NXP 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park * 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park #ifndef SCFG_H 9*54fd6939SJiyong Park #define SCFG_H 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park #ifdef CONFIG_CHASSIS_2 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park /* SCFG register offsets */ 14*54fd6939SJiyong Park #define SCFG_CORE0_SFT_RST_OFFSET 0x0130 15*54fd6939SJiyong Park #define SCFG_SNPCNFGCR_OFFSET 0x01A4 16*54fd6939SJiyong Park #define SCFG_CORESRENCR_OFFSET 0x0204 17*54fd6939SJiyong Park #define SCFG_RVBAR0_0_OFFSET 0x0220 18*54fd6939SJiyong Park #define SCFG_RVBAR0_1_OFFSET 0x0224 19*54fd6939SJiyong Park #define SCFG_COREBCR_OFFSET 0x0680 20*54fd6939SJiyong Park #define SCFG_RETREQCR_OFFSET 0x0424 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park #define SCFG_COREPMCR_OFFSET 0x042C 23*54fd6939SJiyong Park #define COREPMCR_WFIL2 0x1 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park #define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188 26*54fd6939SJiyong Park #define SCFG_BOOTLOCPTRH_OFFSET 0x0600 27*54fd6939SJiyong Park #define SCFG_BOOTLOCPTRL_OFFSET 0x0604 28*54fd6939SJiyong Park #define SCFG_SCRATCHRW2_OFFSET 0x0608 29*54fd6939SJiyong Park #define SCFG_SCRATCHRW3_OFFSET 0x060C 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park /* SCFG bit fields */ 32*54fd6939SJiyong Park #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 33*54fd6939SJiyong Park #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 34*54fd6939SJiyong Park #endif /* CONFIG_CHASSIS_2 */ 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park #ifndef __ASSEMBLER__ 37*54fd6939SJiyong Park #include <endian.h> 38*54fd6939SJiyong Park #include <lib/mmio.h> 39*54fd6939SJiyong Park 40*54fd6939SJiyong Park #ifdef NXP_SCFG_BE 41*54fd6939SJiyong Park #define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 42*54fd6939SJiyong Park #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 43*54fd6939SJiyong Park #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) 44*54fd6939SJiyong Park #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) 45*54fd6939SJiyong Park #define scfg_clrsetbits32(a, clear, set) \ 46*54fd6939SJiyong Park mmio_clrsetbits_32((uintptr_t)(a), clear, set) 47*54fd6939SJiyong Park #elif defined(NXP_SCFG_LE) 48*54fd6939SJiyong Park #define scfg_in32(a) mmio_read_32((uintptr_t)(a)) 49*54fd6939SJiyong Park #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v) 50*54fd6939SJiyong Park #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) 51*54fd6939SJiyong Park #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) 52*54fd6939SJiyong Park #define scfg_clrsetbits32(a, clear, set) \ 53*54fd6939SJiyong Park mmio_clrsetbits_32((uintptr_t)(a), clear, set) 54*54fd6939SJiyong Park #else 55*54fd6939SJiyong Park #error Please define CCSR SCFG register endianness 56*54fd6939SJiyong Park #endif 57*54fd6939SJiyong Park #endif /* __ASSEMBLER__ */ 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park #endif /* SCFG_H */ 60