1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright 2021 NXP 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park * 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park #ifndef DDR_OPTS_H 9*54fd6939SJiyong Park #define DDR_OPTS_H 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park #define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */ 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #define DDR_BC4 4 /* burst chop */ 14*54fd6939SJiyong Park #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 15*54fd6939SJiyong Park #define DDR_BL8 8 /* burst length 8 */ 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park #define DDR4_RTT_OFF 0 18*54fd6939SJiyong Park #define DDR4_RTT_60_OHM 1 /* RZQ/4 */ 19*54fd6939SJiyong Park #define DDR4_RTT_120_OHM 2 /* RZQ/2 */ 20*54fd6939SJiyong Park #define DDR4_RTT_40_OHM 3 /* RZQ/6 */ 21*54fd6939SJiyong Park #define DDR4_RTT_240_OHM 4 /* RZQ/1 */ 22*54fd6939SJiyong Park #define DDR4_RTT_48_OHM 5 /* RZQ/5 */ 23*54fd6939SJiyong Park #define DDR4_RTT_80_OHM 6 /* RZQ/3 */ 24*54fd6939SJiyong Park #define DDR4_RTT_34_OHM 7 /* RZQ/7 */ 25*54fd6939SJiyong Park #define DDR4_RTT_WR_OFF 0 26*54fd6939SJiyong Park #define DDR4_RTT_WR_120_OHM 1 27*54fd6939SJiyong Park #define DDR4_RTT_WR_240_OHM 2 28*54fd6939SJiyong Park #define DDR4_RTT_WR_HZ 3 29*54fd6939SJiyong Park #define DDR4_RTT_WR_80_OHM 4 30*54fd6939SJiyong Park #define DDR_ODT_NEVER 0x0 31*54fd6939SJiyong Park #define DDR_ODT_CS 0x1 32*54fd6939SJiyong Park #define DDR_ODT_ALL_OTHER_CS 0x2 33*54fd6939SJiyong Park #define DDR_ODT_OTHER_DIMM 0x3 34*54fd6939SJiyong Park #define DDR_ODT_ALL 0x4 35*54fd6939SJiyong Park #define DDR_ODT_SAME_DIMM 0x5 36*54fd6939SJiyong Park #define DDR_ODT_CS_AND_OTHER_DIMM 0x6 37*54fd6939SJiyong Park #define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 38*54fd6939SJiyong Park #define DDR_BA_INTLV_CS01 0x40 39*54fd6939SJiyong Park #define DDR_BA_INTLV_CS0123 0x64 40*54fd6939SJiyong Park #define DDR_BA_NONE 0 41*54fd6939SJiyong Park #define DDR_256B_INTLV 0x8 42*54fd6939SJiyong Park 43*54fd6939SJiyong Park struct memctl_opt { 44*54fd6939SJiyong Park int rdimm; 45*54fd6939SJiyong Park unsigned int dbw_cap_shift; 46*54fd6939SJiyong Park struct local_opts_s { 47*54fd6939SJiyong Park unsigned int auto_precharge; 48*54fd6939SJiyong Park unsigned int odt_rd_cfg; 49*54fd6939SJiyong Park unsigned int odt_wr_cfg; 50*54fd6939SJiyong Park unsigned int odt_rtt_norm; 51*54fd6939SJiyong Park unsigned int odt_rtt_wr; 52*54fd6939SJiyong Park } cs_odt[DDRC_NUM_CS]; 53*54fd6939SJiyong Park int ctlr_intlv; 54*54fd6939SJiyong Park unsigned int ctlr_intlv_mode; 55*54fd6939SJiyong Park unsigned int ba_intlv; 56*54fd6939SJiyong Park int addr_hash; 57*54fd6939SJiyong Park int ecc_mode; 58*54fd6939SJiyong Park int ctlr_init_ecc; 59*54fd6939SJiyong Park int self_refresh_in_sleep; 60*54fd6939SJiyong Park int self_refresh_irq_en; 61*54fd6939SJiyong Park int dynamic_power; 62*54fd6939SJiyong Park /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ 63*54fd6939SJiyong Park unsigned int data_bus_dimm; 64*54fd6939SJiyong Park unsigned int data_bus_used; /* on individual board */ 65*54fd6939SJiyong Park unsigned int burst_length; /* BC4, OTF and BL8 */ 66*54fd6939SJiyong Park int otf_burst_chop_en; 67*54fd6939SJiyong Park int mirrored_dimm; 68*54fd6939SJiyong Park int quad_rank_present; 69*54fd6939SJiyong Park int output_driver_impedance; 70*54fd6939SJiyong Park int ap_en; 71*54fd6939SJiyong Park int x4_en; 72*54fd6939SJiyong Park 73*54fd6939SJiyong Park int caslat_override; 74*54fd6939SJiyong Park unsigned int caslat_override_value; 75*54fd6939SJiyong Park int addt_lat_override; 76*54fd6939SJiyong Park unsigned int addt_lat_override_value; 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park unsigned int clk_adj; 79*54fd6939SJiyong Park unsigned int cpo_sample; 80*54fd6939SJiyong Park unsigned int wr_data_delay; 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park unsigned int cswl_override; 83*54fd6939SJiyong Park unsigned int wrlvl_override; 84*54fd6939SJiyong Park unsigned int wrlvl_sample; 85*54fd6939SJiyong Park unsigned int wrlvl_start; 86*54fd6939SJiyong Park unsigned int wrlvl_ctl_2; 87*54fd6939SJiyong Park unsigned int wrlvl_ctl_3; 88*54fd6939SJiyong Park 89*54fd6939SJiyong Park int half_strength_drive_en; 90*54fd6939SJiyong Park int twot_en; 91*54fd6939SJiyong Park int threet_en; 92*54fd6939SJiyong Park unsigned int bstopre; 93*54fd6939SJiyong Park unsigned int tfaw_ps; 94*54fd6939SJiyong Park 95*54fd6939SJiyong Park int rtt_override; 96*54fd6939SJiyong Park unsigned int rtt_override_value; 97*54fd6939SJiyong Park unsigned int rtt_wr_override_value; 98*54fd6939SJiyong Park unsigned int rtt_park; 99*54fd6939SJiyong Park 100*54fd6939SJiyong Park int auto_self_refresh_en; 101*54fd6939SJiyong Park unsigned int sr_it; 102*54fd6939SJiyong Park unsigned int ddr_cdr1; 103*54fd6939SJiyong Park unsigned int ddr_cdr2; 104*54fd6939SJiyong Park 105*54fd6939SJiyong Park unsigned int trwt_override; 106*54fd6939SJiyong Park unsigned int trwt; 107*54fd6939SJiyong Park unsigned int twrt; 108*54fd6939SJiyong Park unsigned int trrt; 109*54fd6939SJiyong Park unsigned int twwt; 110*54fd6939SJiyong Park 111*54fd6939SJiyong Park unsigned int vref_phy; 112*54fd6939SJiyong Park unsigned int vref_dimm; 113*54fd6939SJiyong Park unsigned int odt; 114*54fd6939SJiyong Park unsigned int phy_tx_impedance; 115*54fd6939SJiyong Park unsigned int phy_atx_impedance; 116*54fd6939SJiyong Park unsigned int skip2d; 117*54fd6939SJiyong Park }; 118*54fd6939SJiyong Park 119*54fd6939SJiyong Park #endif /* DDR_OPTS_H */ 120