1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright 2021 NXP 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park * 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park #ifndef DDR_REG_H 9*54fd6939SJiyong Park #define DDR_REG_H 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park #define SDRAM_CS_CONFIG_EN 0x80000000 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 14*54fd6939SJiyong Park */ 15*54fd6939SJiyong Park #define SDRAM_CFG_MEM_EN 0x80000000 16*54fd6939SJiyong Park #define SDRAM_CFG_SREN 0x40000000 17*54fd6939SJiyong Park #define SDRAM_CFG_ECC_EN 0x20000000 18*54fd6939SJiyong Park #define SDRAM_CFG_RD_EN 0x10000000 19*54fd6939SJiyong Park #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 20*54fd6939SJiyong Park #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 21*54fd6939SJiyong Park #define SDRAM_CFG_DYN_PWR 0x00200000 22*54fd6939SJiyong Park #define SDRAM_CFG_DBW_MASK 0x00180000 23*54fd6939SJiyong Park #define SDRAM_CFG_DBW_SHIFT 19 24*54fd6939SJiyong Park #define SDRAM_CFG_32_BW 0x00080000 25*54fd6939SJiyong Park #define SDRAM_CFG_16_BW 0x00100000 26*54fd6939SJiyong Park #define SDRAM_CFG_8_BW 0x00180000 27*54fd6939SJiyong Park #define SDRAM_CFG_8_BE 0x00040000 28*54fd6939SJiyong Park #define SDRAM_CFG_2T_EN 0x00008000 29*54fd6939SJiyong Park #define SDRAM_CFG_MEM_HLT 0x00000002 30*54fd6939SJiyong Park #define SDRAM_CFG_BI 0x00000001 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park #define SDRAM_CFG2_FRC_SR 0x80000000 33*54fd6939SJiyong Park #define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR) 34*54fd6939SJiyong Park #define SDRAM_CFG2_D_INIT 0x00000010 35*54fd6939SJiyong Park #define SDRAM_CFG2_AP_EN 0x00000020 36*54fd6939SJiyong Park #define SDRAM_CFG2_ODT_ONLY_READ 2 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park #define SDRAM_CFG3_DDRC_RST 0x80000000 39*54fd6939SJiyong Park 40*54fd6939SJiyong Park #define SDRAM_INTERVAL_REFINT 0xFFFF0000 41*54fd6939SJiyong Park #define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT) 42*54fd6939SJiyong Park #define SDRAM_INTERVAL_BSTOPRE 0x3FFF 43*54fd6939SJiyong Park 44*54fd6939SJiyong Park /* DDR_MD_CNTL */ 45*54fd6939SJiyong Park #define MD_CNTL_MD_EN 0x80000000 46*54fd6939SJiyong Park #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) 47*54fd6939SJiyong Park #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) 48*54fd6939SJiyong Park #define MD_CNTL_CKE(x) (((x) & 0x3) << 20) 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park /* DDR_CDR1 */ 51*54fd6939SJiyong Park #define DDR_CDR1_DHC_EN 0x80000000 52*54fd6939SJiyong Park #define DDR_CDR1_ODT_SHIFT 17 53*54fd6939SJiyong Park #define DDR_CDR1_ODT_MASK 0x6 54*54fd6939SJiyong Park #define DDR_CDR2_ODT_MASK 0x1 55*54fd6939SJiyong Park #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) 56*54fd6939SJiyong Park #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) 57*54fd6939SJiyong Park #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) 58*54fd6939SJiyong Park #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 59*54fd6939SJiyong Park #define DDR_CDR2_VREF_RANGE_2 0x00000040 60*54fd6939SJiyong Park #define DDR_CDR_ODT_OFF 0x0 61*54fd6939SJiyong Park #define DDR_CDR_ODT_100ohm 0x1 62*54fd6939SJiyong Park #define DDR_CDR_ODT_120OHM 0x2 63*54fd6939SJiyong Park #define DDR_CDR_ODT_80ohm 0x3 64*54fd6939SJiyong Park #define DDR_CDR_ODT_60ohm 0x4 65*54fd6939SJiyong Park #define DDR_CDR_ODT_40ohm 0x5 66*54fd6939SJiyong Park #define DDR_CDR_ODT_50ohm 0x6 67*54fd6939SJiyong Park #define DDR_CDR_ODT_30ohm 0x7 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park /* DDR ERR_DISABLE */ 71*54fd6939SJiyong Park #define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ 72*54fd6939SJiyong Park #define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */ 73*54fd6939SJiyong Park #define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */ 74*54fd6939SJiyong Park 75*54fd6939SJiyong Park /* Mode Registers */ 76*54fd6939SJiyong Park #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ 77*54fd6939SJiyong Park #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ 78*54fd6939SJiyong Park 79*54fd6939SJiyong Park /* DDR DSR2 register */ 80*54fd6939SJiyong Park #define DDR_DSR_2_PHY_INIT_CMPLT 0x4 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park /* SDRAM TIMING_CFG_10 register */ 83*54fd6939SJiyong Park #define DDR_TIMING_CFG_10_T_STAB 0x7FFF 84*54fd6939SJiyong Park 85*54fd6939SJiyong Park /* DEBUG 2 register */ 86*54fd6939SJiyong Park #define DDR_DBG_2_MEM_IDLE 0x00000002 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park /* DEBUG 26 register */ 89*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_6 (0x1 << 6) 90*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_7 (0x1 << 7) 91*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_12 (0x1 << 12) 92*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_13 (0x1 << 13) 93*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_14 (0x1 << 14) 94*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_15 (0x1 << 15) 95*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_16 (0x1 << 16) 96*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_17 (0x1 << 17) 97*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_18 (0x1 << 18) 98*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_19 (0x1 << 19) 99*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_24 (0x1 << 24) 100*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_25 (0x1 << 25) 101*54fd6939SJiyong Park 102*54fd6939SJiyong Park #define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24) 103*54fd6939SJiyong Park 104*54fd6939SJiyong Park /* DEBUG_29 register */ 105*54fd6939SJiyong Park #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ 106*54fd6939SJiyong Park 107*54fd6939SJiyong Park #define DDR_INIT_ADDR_EXT_UIA (1 << 31) 108*54fd6939SJiyong Park 109*54fd6939SJiyong Park #endif /* DDR_REG_H */ 110