1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright 2021 NXP 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park * 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park #ifndef QSPI_H 9*54fd6939SJiyong Park #define QSPI_H 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park #include <endian.h> 12*54fd6939SJiyong Park #include <lib/mmio.h> 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park #define CHS_QSPI_MCR 0x01550000 15*54fd6939SJiyong Park #define CHS_QSPI_64LE 0xC 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park #ifdef NXP_QSPI_BE 18*54fd6939SJiyong Park #define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 19*54fd6939SJiyong Park #define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 20*54fd6939SJiyong Park #elif defined(NXP_QSPI_LE) 21*54fd6939SJiyong Park #define qspi_in32(a) mmio_read_32((uintptr_t)(a)) 22*54fd6939SJiyong Park #define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) 23*54fd6939SJiyong Park #else 24*54fd6939SJiyong Park #error Please define CCSR QSPI register endianness 25*54fd6939SJiyong Park #endif 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park int qspi_io_setup(uintptr_t nxp_qspi_flash_addr, 28*54fd6939SJiyong Park size_t nxp_qspi_flash_size, 29*54fd6939SJiyong Park uintptr_t fip_offset); 30*54fd6939SJiyong Park #endif /* __QSPI_H__ */ 31