1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef DRIVERS_SPI_NAND_H 8*54fd6939SJiyong Park #define DRIVERS_SPI_NAND_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <drivers/nand.h> 11*54fd6939SJiyong Park #include <drivers/spi_mem.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #define SPI_NAND_OP_GET_FEATURE 0x0FU 14*54fd6939SJiyong Park #define SPI_NAND_OP_SET_FEATURE 0x1FU 15*54fd6939SJiyong Park #define SPI_NAND_OP_READ_ID 0x9FU 16*54fd6939SJiyong Park #define SPI_NAND_OP_LOAD_PAGE 0x13U 17*54fd6939SJiyong Park #define SPI_NAND_OP_RESET 0xFFU 18*54fd6939SJiyong Park #define SPI_NAND_OP_READ_FROM_CACHE 0x03U 19*54fd6939SJiyong Park #define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU 20*54fd6939SJiyong Park #define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park /* Configuration register */ 23*54fd6939SJiyong Park #define SPI_NAND_REG_CFG 0xB0U 24*54fd6939SJiyong Park #define SPI_NAND_CFG_ECC_EN BIT(4) 25*54fd6939SJiyong Park #define SPI_NAND_CFG_QE BIT(0) 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park /* Status register */ 28*54fd6939SJiyong Park #define SPI_NAND_REG_STATUS 0xC0U 29*54fd6939SJiyong Park #define SPI_NAND_STATUS_BUSY BIT(0) 30*54fd6939SJiyong Park #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park struct spinand_device { 33*54fd6939SJiyong Park struct nand_device *nand_dev; 34*54fd6939SJiyong Park struct spi_mem_op spi_read_cache_op; 35*54fd6939SJiyong Park uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ 36*54fd6939SJiyong Park }; 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park int spi_nand_init(unsigned long long *size, unsigned int *erase_size); 39*54fd6939SJiyong Park 40*54fd6939SJiyong Park /* 41*54fd6939SJiyong Park * Platform can implement this to override default SPI-NAND instance 42*54fd6939SJiyong Park * configuration. 43*54fd6939SJiyong Park * 44*54fd6939SJiyong Park * @device: target SPI-NAND instance. 45*54fd6939SJiyong Park * Return 0 on success, negative value otherwise. 46*54fd6939SJiyong Park */ 47*54fd6939SJiyong Park int plat_get_spi_nand_data(struct spinand_device *device); 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park #endif /* DRIVERS_SPI_NAND_H */ 50