1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: MIT 5*54fd6939SJiyong Park * 6*54fd6939SJiyong Park * This header provides constants for the ARM GIC. 7*54fd6939SJiyong Park */ 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 10*54fd6939SJiyong Park #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park #include <dt-bindings/interrupt-controller/irq.h> 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park /* interrupt specifier cell 0 */ 15*54fd6939SJiyong Park 16*54fd6939SJiyong Park #define GIC_SPI 0 17*54fd6939SJiyong Park #define GIC_PPI 1 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park /* 20*54fd6939SJiyong Park * Interrupt specifier cell 2. 21*54fd6939SJiyong Park * The flags in irq.h are valid, plus those below. 22*54fd6939SJiyong Park */ 23*54fd6939SJiyong Park #define GIC_CPU_MASK_RAW(x) ((x) << 8) 24*54fd6939SJiyong Park #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park #endif 27