1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #include <stdbool.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park #include <arch.h> 10*54fd6939SJiyong Park #include <arch_helpers.h> 11*54fd6939SJiyong Park #include <lib/el3_runtime/pubsub.h> 12*54fd6939SJiyong Park #include <lib/extensions/sve.h> 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park /* 15*54fd6939SJiyong Park * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. 16*54fd6939SJiyong Park * VECTOR_SIZE = (LEN+1) * 128 17*54fd6939SJiyong Park */ 18*54fd6939SJiyong Park #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) 19*54fd6939SJiyong Park sve_supported(void)20*54fd6939SJiyong Parkstatic bool sve_supported(void) 21*54fd6939SJiyong Park { 22*54fd6939SJiyong Park uint64_t features; 23*54fd6939SJiyong Park 24*54fd6939SJiyong Park features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; 25*54fd6939SJiyong Park return (features & ID_AA64PFR0_SVE_MASK) == 1U; 26*54fd6939SJiyong Park } 27*54fd6939SJiyong Park sve_enable(cpu_context_t * context)28*54fd6939SJiyong Parkvoid sve_enable(cpu_context_t *context) 29*54fd6939SJiyong Park { 30*54fd6939SJiyong Park u_register_t cptr_el3; 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park if (!sve_supported()) { 33*54fd6939SJiyong Park return; 34*54fd6939SJiyong Park } 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park /* Enable access to SVE functionality for all ELs. */ 39*54fd6939SJiyong Park cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); 40*54fd6939SJiyong Park write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park /* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */ 43*54fd6939SJiyong Park write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, 44*54fd6939SJiyong Park (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512))); 45*54fd6939SJiyong Park } 46*54fd6939SJiyong Park sve_disable(cpu_context_t * context)47*54fd6939SJiyong Parkvoid sve_disable(cpu_context_t *context) 48*54fd6939SJiyong Park { 49*54fd6939SJiyong Park u_register_t reg; 50*54fd6939SJiyong Park el3_state_t *state; 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park /* Make sure SME is implemented in hardware before continuing. */ 53*54fd6939SJiyong Park if (!sve_supported()) { 54*54fd6939SJiyong Park return; 55*54fd6939SJiyong Park } 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park /* Get the context state. */ 58*54fd6939SJiyong Park state = get_el3state_ctx(context); 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park /* Disable SVE and FPU since they share registers. */ 61*54fd6939SJiyong Park reg = read_ctx_reg(state, CTX_CPTR_EL3); 62*54fd6939SJiyong Park reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 63*54fd6939SJiyong Park reg |= TFP_BIT; /* Trap FPU/SIMD */ 64*54fd6939SJiyong Park write_ctx_reg(state, CTX_CPTR_EL3, reg); 65*54fd6939SJiyong Park } 66