1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <lib/xlat_tables/xlat_tables_defs.h> 8*54fd6939SJiyong Park#include <platform_def.h> 9*54fd6939SJiyong Park 10*54fd6939SJiyong ParkMEMORY { 11*54fd6939SJiyong Park ROM (rx): ORIGIN = ROMLIB_RO_BASE, LENGTH = ROMLIB_RO_LIMIT - ROMLIB_RO_BASE 12*54fd6939SJiyong Park RAM (rwx): ORIGIN = ROMLIB_RW_BASE, LENGTH = ROMLIB_RW_END - ROMLIB_RW_BASE 13*54fd6939SJiyong Park} 14*54fd6939SJiyong Park 15*54fd6939SJiyong ParkOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 16*54fd6939SJiyong ParkOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 17*54fd6939SJiyong ParkENTRY(jmptbl) 18*54fd6939SJiyong Park 19*54fd6939SJiyong ParkSECTIONS 20*54fd6939SJiyong Park{ 21*54fd6939SJiyong Park . = ROMLIB_RO_BASE; 22*54fd6939SJiyong Park .text : { 23*54fd6939SJiyong Park *jmptbl.o(.text) 24*54fd6939SJiyong Park *(.text*) 25*54fd6939SJiyong Park *(.rodata*) 26*54fd6939SJiyong Park } >ROM 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park __DATA_ROM_START__ = LOADADDR(.data); 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park .data : { 31*54fd6939SJiyong Park __DATA_RAM_START__ = .; 32*54fd6939SJiyong Park *(.data*) 33*54fd6939SJiyong Park __DATA_RAM_END__ = .; 34*54fd6939SJiyong Park } >RAM AT>ROM 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park __DATA_SIZE__ = SIZEOF(.data); 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park .bss : { 39*54fd6939SJiyong Park __BSS_START__ = .; 40*54fd6939SJiyong Park *(.bss*) 41*54fd6939SJiyong Park __BSS_END__ = .; 42*54fd6939SJiyong Park } >RAM 43*54fd6939SJiyong Park __BSS_SIZE__ = SIZEOF(.bss); 44*54fd6939SJiyong Park} 45