1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <drivers/arm/gicv3.h>
8*54fd6939SJiyong Park #include <plat/common/platform.h>
9*54fd6939SJiyong Park
10*54fd6939SJiyong Park #include <platform_def.h>
11*54fd6939SJiyong Park
12*54fd6939SJiyong Park /* The GICv3 driver only needs to be initialized in EL3 */
13*54fd6939SJiyong Park static uintptr_t brcm_rdistif_base_addrs[PLATFORM_CORE_COUNT];
14*54fd6939SJiyong Park
15*54fd6939SJiyong Park static const interrupt_prop_t brcm_interrupt_props[] = {
16*54fd6939SJiyong Park /* G1S interrupts */
17*54fd6939SJiyong Park PLAT_BRCM_G1S_IRQ_PROPS(INTR_GROUP1S),
18*54fd6939SJiyong Park /* G0 interrupts */
19*54fd6939SJiyong Park PLAT_BRCM_G0_IRQ_PROPS(INTR_GROUP0)
20*54fd6939SJiyong Park };
21*54fd6939SJiyong Park
22*54fd6939SJiyong Park /*
23*54fd6939SJiyong Park * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
24*54fd6939SJiyong Park * to core position.
25*54fd6939SJiyong Park *
26*54fd6939SJiyong Park * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
27*54fd6939SJiyong Park * values read from GICR_TYPER don't have an MT field. To reuse the same
28*54fd6939SJiyong Park * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
29*54fd6939SJiyong Park * that read from GICR_TYPER.
30*54fd6939SJiyong Park *
31*54fd6939SJiyong Park * Assumptions:
32*54fd6939SJiyong Park *
33*54fd6939SJiyong Park * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
34*54fd6939SJiyong Park * - No CPUs implemented in the system use affinity level 3.
35*54fd6939SJiyong Park */
brcm_gicv3_mpidr_hash(u_register_t mpidr)36*54fd6939SJiyong Park static unsigned int brcm_gicv3_mpidr_hash(u_register_t mpidr)
37*54fd6939SJiyong Park {
38*54fd6939SJiyong Park mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
39*54fd6939SJiyong Park return plat_core_pos_by_mpidr(mpidr);
40*54fd6939SJiyong Park }
41*54fd6939SJiyong Park
42*54fd6939SJiyong Park static const gicv3_driver_data_t brcm_gic_data = {
43*54fd6939SJiyong Park .gicd_base = PLAT_BRCM_GICD_BASE,
44*54fd6939SJiyong Park .gicr_base = PLAT_BRCM_GICR_BASE,
45*54fd6939SJiyong Park .interrupt_props = brcm_interrupt_props,
46*54fd6939SJiyong Park .interrupt_props_num = ARRAY_SIZE(brcm_interrupt_props),
47*54fd6939SJiyong Park .rdistif_num = PLATFORM_CORE_COUNT,
48*54fd6939SJiyong Park .rdistif_base_addrs = brcm_rdistif_base_addrs,
49*54fd6939SJiyong Park .mpidr_to_core_pos = brcm_gicv3_mpidr_hash
50*54fd6939SJiyong Park };
51*54fd6939SJiyong Park
plat_brcm_gic_driver_init(void)52*54fd6939SJiyong Park void plat_brcm_gic_driver_init(void)
53*54fd6939SJiyong Park {
54*54fd6939SJiyong Park /* TODO Check if this is required to be initialized here
55*54fd6939SJiyong Park * after getting initialized in EL3, should we re-init this here
56*54fd6939SJiyong Park * in S-EL1
57*54fd6939SJiyong Park */
58*54fd6939SJiyong Park gicv3_driver_init(&brcm_gic_data);
59*54fd6939SJiyong Park }
60*54fd6939SJiyong Park
plat_brcm_gic_init(void)61*54fd6939SJiyong Park void plat_brcm_gic_init(void)
62*54fd6939SJiyong Park {
63*54fd6939SJiyong Park gicv3_distif_init();
64*54fd6939SJiyong Park gicv3_rdistif_init(plat_my_core_pos());
65*54fd6939SJiyong Park gicv3_cpuif_enable(plat_my_core_pos());
66*54fd6939SJiyong Park }
67*54fd6939SJiyong Park
plat_brcm_gic_cpuif_enable(void)68*54fd6939SJiyong Park void plat_brcm_gic_cpuif_enable(void)
69*54fd6939SJiyong Park {
70*54fd6939SJiyong Park gicv3_cpuif_enable(plat_my_core_pos());
71*54fd6939SJiyong Park }
72*54fd6939SJiyong Park
plat_brcm_gic_cpuif_disable(void)73*54fd6939SJiyong Park void plat_brcm_gic_cpuif_disable(void)
74*54fd6939SJiyong Park {
75*54fd6939SJiyong Park gicv3_cpuif_disable(plat_my_core_pos());
76*54fd6939SJiyong Park }
77*54fd6939SJiyong Park
plat_brcm_gic_pcpu_init(void)78*54fd6939SJiyong Park void plat_brcm_gic_pcpu_init(void)
79*54fd6939SJiyong Park {
80*54fd6939SJiyong Park gicv3_rdistif_init(plat_my_core_pos());
81*54fd6939SJiyong Park }
82*54fd6939SJiyong Park
plat_brcm_gic_redistif_on(void)83*54fd6939SJiyong Park void plat_brcm_gic_redistif_on(void)
84*54fd6939SJiyong Park {
85*54fd6939SJiyong Park gicv3_rdistif_on(plat_my_core_pos());
86*54fd6939SJiyong Park }
87*54fd6939SJiyong Park
plat_brcm_gic_redistif_off(void)88*54fd6939SJiyong Park void plat_brcm_gic_redistif_off(void)
89*54fd6939SJiyong Park {
90*54fd6939SJiyong Park gicv3_rdistif_off(plat_my_core_pos());
91*54fd6939SJiyong Park }
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