1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <asm_macros.S> 8*54fd6939SJiyong Park#include <platform_def.h> 9*54fd6939SJiyong Park#include <cortex_a35.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park .globl plat_is_my_cpu_primary 12*54fd6939SJiyong Park .globl plat_my_core_pos 13*54fd6939SJiyong Park .globl plat_calc_core_pos 14*54fd6939SJiyong Park .globl plat_reset_handler 15*54fd6939SJiyong Park .globl plat_get_my_entrypoint 16*54fd6939SJiyong Park .globl plat_secondary_cold_boot_setup 17*54fd6939SJiyong Park .globl plat_crash_console_init 18*54fd6939SJiyong Park .globl plat_crash_console_putc 19*54fd6939SJiyong Park .globl plat_crash_console_flush 20*54fd6939SJiyong Park .globl platform_mem_init 21*54fd6939SJiyong Park .globl imx_mailbox_init 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park /* -------------------------------------------------------------------- 24*54fd6939SJiyong Park * Helper macro that reads the part number of the current CPU and jumps 25*54fd6939SJiyong Park * to the given label if it matches the CPU MIDR provided. 26*54fd6939SJiyong Park * 27*54fd6939SJiyong Park * Clobbers x0. 28*54fd6939SJiyong Park * -------------------------------------------------------------------- 29*54fd6939SJiyong Park */ 30*54fd6939SJiyong Park .macro jump_if_cpu_midr _cpu_midr, _label 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park mrs x0, midr_el1 33*54fd6939SJiyong Park ubfx x0, x0, MIDR_PN_SHIFT, #12 34*54fd6939SJiyong Park cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 35*54fd6939SJiyong Park b.eq \_label 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park .endm 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park /* ---------------------------------------------- 40*54fd6939SJiyong Park * The mailbox_base is used to distinguish warm/cold 41*54fd6939SJiyong Park * reset. The mailbox_base is in the data section, not 42*54fd6939SJiyong Park * in .bss, this allows function to start using this 43*54fd6939SJiyong Park * variable before the runtime memory is initialized. 44*54fd6939SJiyong Park * ---------------------------------------------- 45*54fd6939SJiyong Park */ 46*54fd6939SJiyong Park .section .data.mailbox_base 47*54fd6939SJiyong Park .align 3 48*54fd6939SJiyong Park mailbox_base: .quad 0x0 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park /* ---------------------------------------------- 51*54fd6939SJiyong Park * unsigned int plat_is_my_cpu_primary(void); 52*54fd6939SJiyong Park * This function checks if this is the primary CPU 53*54fd6939SJiyong Park * ---------------------------------------------- 54*54fd6939SJiyong Park */ 55*54fd6939SJiyong Parkfunc plat_is_my_cpu_primary 56*54fd6939SJiyong Park mrs x0, mpidr_el1 57*54fd6939SJiyong Park and x0, x0, #(MPIDR_CPU_MASK) 58*54fd6939SJiyong Park cmp x0, #PLAT_PRIMARY_CPU 59*54fd6939SJiyong Park cset x0, eq 60*54fd6939SJiyong Park ret 61*54fd6939SJiyong Parkendfunc plat_is_my_cpu_primary 62*54fd6939SJiyong Park 63*54fd6939SJiyong Park /* ---------------------------------------------- 64*54fd6939SJiyong Park * unsigned int plat_my_core_pos(void) 65*54fd6939SJiyong Park * This Function uses the plat_calc_core_pos() 66*54fd6939SJiyong Park * to get the index of the calling CPU. 67*54fd6939SJiyong Park * ---------------------------------------------- 68*54fd6939SJiyong Park */ 69*54fd6939SJiyong Parkfunc plat_my_core_pos 70*54fd6939SJiyong Park mrs x0, mpidr_el1 71*54fd6939SJiyong Park and x1, x0, #MPIDR_CPU_MASK 72*54fd6939SJiyong Park and x0, x0, #MPIDR_CLUSTER_MASK 73*54fd6939SJiyong Park add x0, x1, x0, LSR #6 74*54fd6939SJiyong Park ret 75*54fd6939SJiyong Parkendfunc plat_my_core_pos 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park /* 78*54fd6939SJiyong Park * unsigned int plat_calc_core_pos(uint64_t mpidr) 79*54fd6939SJiyong Park * helper function to calculate the core position. 80*54fd6939SJiyong Park * With this function. 81*54fd6939SJiyong Park */ 82*54fd6939SJiyong Parkfunc plat_calc_core_pos 83*54fd6939SJiyong Park and x1, x0, #MPIDR_CPU_MASK 84*54fd6939SJiyong Park and x0, x0, #MPIDR_CLUSTER_MASK 85*54fd6939SJiyong Park add x0, x1, x0, LSR #6 86*54fd6939SJiyong Park ret 87*54fd6939SJiyong Parkendfunc plat_calc_core_pos 88*54fd6939SJiyong Park 89*54fd6939SJiyong Park /* --------------------------------------------- 90*54fd6939SJiyong Park * function to get the entrypoint. 91*54fd6939SJiyong Park * --------------------------------------------- 92*54fd6939SJiyong Park */ 93*54fd6939SJiyong Parkfunc plat_get_my_entrypoint 94*54fd6939SJiyong Park adrp x1, mailbox_base 95*54fd6939SJiyong Park ldr x0, [x1, :lo12:mailbox_base] 96*54fd6939SJiyong Park ret 97*54fd6939SJiyong Parkendfunc plat_get_my_entrypoint 98*54fd6939SJiyong Park 99*54fd6939SJiyong Parkfunc imx_mailbox_init 100*54fd6939SJiyong Park adrp x1, mailbox_base 101*54fd6939SJiyong Park str x0, [x1, :lo12:mailbox_base] 102*54fd6939SJiyong Park ret 103*54fd6939SJiyong Parkendfunc imx_mailbox_init 104*54fd6939SJiyong Park 105*54fd6939SJiyong Parkfunc plat_secondary_cold_boot_setup 106*54fd6939SJiyong Park b . 107*54fd6939SJiyong Parkendfunc plat_secondary_cold_boot_setup 108*54fd6939SJiyong Park 109*54fd6939SJiyong Parkfunc plat_crash_console_init 110*54fd6939SJiyong Park mov x0, #1 111*54fd6939SJiyong Park ret 112*54fd6939SJiyong Parkendfunc plat_crash_console_init 113*54fd6939SJiyong Park 114*54fd6939SJiyong Parkfunc plat_crash_console_putc 115*54fd6939SJiyong Park ret 116*54fd6939SJiyong Parkendfunc plat_crash_console_putc 117*54fd6939SJiyong Park 118*54fd6939SJiyong Parkfunc plat_crash_console_flush 119*54fd6939SJiyong Park mov x0, #0 120*54fd6939SJiyong Park ret 121*54fd6939SJiyong Parkendfunc plat_crash_console_flush 122*54fd6939SJiyong Park 123*54fd6939SJiyong Parkfunc platform_mem_init 124*54fd6939SJiyong Park ret 125*54fd6939SJiyong Parkendfunc platform_mem_init 126