1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #include <arch.h> 8*54fd6939SJiyong Park #include <arch_helpers.h> 9*54fd6939SJiyong Park #include <plat/common/platform.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park const unsigned char imx_power_domain_tree_desc[] = { 12*54fd6939SJiyong Park PWR_DOMAIN_AT_MAX_LVL, 13*54fd6939SJiyong Park PLATFORM_CLUSTER_COUNT, 14*54fd6939SJiyong Park PLATFORM_CLUSTER0_CORE_COUNT, 15*54fd6939SJiyong Park PLATFORM_CLUSTER1_CORE_COUNT, 16*54fd6939SJiyong Park }; 17*54fd6939SJiyong Park plat_get_power_domain_tree_desc(void)18*54fd6939SJiyong Parkconst unsigned char *plat_get_power_domain_tree_desc(void) 19*54fd6939SJiyong Park { 20*54fd6939SJiyong Park return imx_power_domain_tree_desc; 21*54fd6939SJiyong Park } 22*54fd6939SJiyong Park plat_core_pos_by_mpidr(u_register_t mpidr)23*54fd6939SJiyong Parkint plat_core_pos_by_mpidr(u_register_t mpidr) 24*54fd6939SJiyong Park { 25*54fd6939SJiyong Park unsigned int cluster_id, cpu_id; 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park mpidr &= MPIDR_AFFINITY_MASK; 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) 30*54fd6939SJiyong Park return -1; 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 33*54fd6939SJiyong Park cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park if (cluster_id > PLATFORM_CLUSTER_COUNT || 36*54fd6939SJiyong Park cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) 37*54fd6939SJiyong Park return -1; 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park return (cpu_id + (cluster_id * 4)); 40*54fd6939SJiyong Park } 41