1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <lib/mmio.h>
8*54fd6939SJiyong Park #include <lib/utils_def.h>
9*54fd6939SJiyong Park
10*54fd6939SJiyong Park #include <imx_aips.h>
11*54fd6939SJiyong Park #include <imx_regs.h>
12*54fd6939SJiyong Park
imx_aips_set_default_access(struct aipstz_regs * aips_regs)13*54fd6939SJiyong Park static void imx_aips_set_default_access(struct aipstz_regs *aips_regs)
14*54fd6939SJiyong Park {
15*54fd6939SJiyong Park int i;
16*54fd6939SJiyong Park uintptr_t addr;
17*54fd6939SJiyong Park
18*54fd6939SJiyong Park /*
19*54fd6939SJiyong Park * See section 4.7.7.1 AIPSTZ_MPR field descriptions
20*54fd6939SJiyong Park * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
21*54fd6939SJiyong Park * 0111 ->
22*54fd6939SJiyong Park * 0: Write Access from master not buffered
23*54fd6939SJiyong Park * 1: Master is trusted for read access
24*54fd6939SJiyong Park * 1: Master is trsuted for write access
25*54fd6939SJiyong Park * 1: Access from master is not forced to user mode
26*54fd6939SJiyong Park */
27*54fd6939SJiyong Park addr = (uintptr_t)&aips_regs->aipstz_mpr;
28*54fd6939SJiyong Park mmio_write_32(addr, 0x77777777);
29*54fd6939SJiyong Park
30*54fd6939SJiyong Park /*
31*54fd6939SJiyong Park * Helpfully the OPACR registers have the logical inversion of the above
32*54fd6939SJiyong Park * See section 4.7.7.1 AIPSTZ_MPR field descriptions
33*54fd6939SJiyong Park * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
34*54fd6939SJiyong Park * 0000 ->
35*54fd6939SJiyong Park * 0: Write Access to the peripheral is not buffered by AIPSTZ
36*54fd6939SJiyong Park * 0: The peripheral does not require supervisor priv to access
37*54fd6939SJiyong Park * 0: Master is trsuted for write access
38*54fd6939SJiyong Park * 0: Access from master is not forced to user mode
39*54fd6939SJiyong Park */
40*54fd6939SJiyong Park for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) {
41*54fd6939SJiyong Park addr = (uintptr_t)&aips_regs->aipstz_opacr[i];
42*54fd6939SJiyong Park mmio_write_32(addr, 0x00000000);
43*54fd6939SJiyong Park }
44*54fd6939SJiyong Park }
45*54fd6939SJiyong Park
imx_aips_init(void)46*54fd6939SJiyong Park void imx_aips_init(void)
47*54fd6939SJiyong Park {
48*54fd6939SJiyong Park int i;
49*54fd6939SJiyong Park struct aipstz_regs *aips_regs[] = {
50*54fd6939SJiyong Park (struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET),
51*54fd6939SJiyong Park (struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET),
52*54fd6939SJiyong Park (struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET),
53*54fd6939SJiyong Park };
54*54fd6939SJiyong Park
55*54fd6939SJiyong Park for (i = 0; i < ARRAY_SIZE(aips_regs); i++)
56*54fd6939SJiyong Park imx_aips_set_default_access(aips_regs[i]);
57*54fd6939SJiyong Park }
58