1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2019, NXP. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <lib/mmio.h>
8*54fd6939SJiyong Park
9*54fd6939SJiyong Park #include <imx8m_caam.h>
10*54fd6939SJiyong Park
imx8m_caam_init(void)11*54fd6939SJiyong Park void imx8m_caam_init(void)
12*54fd6939SJiyong Park {
13*54fd6939SJiyong Park uint32_t sm_cmd;
14*54fd6939SJiyong Park
15*54fd6939SJiyong Park /* Dealloc part 0 and 2 with current DID */
16*54fd6939SJiyong Park sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
17*54fd6939SJiyong Park mmio_write_32(SM_CMD, sm_cmd);
18*54fd6939SJiyong Park
19*54fd6939SJiyong Park sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
20*54fd6939SJiyong Park mmio_write_32(SM_CMD, sm_cmd);
21*54fd6939SJiyong Park
22*54fd6939SJiyong Park /* config CAAM JRaMID set MID to Cortex A */
23*54fd6939SJiyong Park mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
24*54fd6939SJiyong Park mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
25*54fd6939SJiyong Park mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park /* Alloc partition 0 writing SMPO and SMAGs */
28*54fd6939SJiyong Park mmio_write_32(SM_P0_PERM, 0xff);
29*54fd6939SJiyong Park mmio_write_32(SM_P0_SMAG2, 0xffffffff);
30*54fd6939SJiyong Park mmio_write_32(SM_P0_SMAG1, 0xffffffff);
31*54fd6939SJiyong Park
32*54fd6939SJiyong Park /* Allocate page 0 and 1 to partition 0 with DID set */
33*54fd6939SJiyong Park sm_cmd = (0 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
34*54fd6939SJiyong Park SMC_CMD_ALLOC_PAGE);
35*54fd6939SJiyong Park mmio_write_32(SM_CMD, sm_cmd);
36*54fd6939SJiyong Park
37*54fd6939SJiyong Park sm_cmd = (1 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
38*54fd6939SJiyong Park SMC_CMD_ALLOC_PAGE);
39*54fd6939SJiyong Park mmio_write_32(SM_CMD, sm_cmd);
40*54fd6939SJiyong Park }
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