1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <stdlib.h>
8*54fd6939SJiyong Park #include <stdint.h>
9*54fd6939SJiyong Park #include <stdbool.h>
10*54fd6939SJiyong Park
11*54fd6939SJiyong Park #include <common/debug.h>
12*54fd6939SJiyong Park #include <drivers/delay_timer.h>
13*54fd6939SJiyong Park #include <lib/mmio.h>
14*54fd6939SJiyong Park #include <lib/psci/psci.h>
15*54fd6939SJiyong Park #include <lib/smccc.h>
16*54fd6939SJiyong Park #include <platform_def.h>
17*54fd6939SJiyong Park #include <services/std_svc.h>
18*54fd6939SJiyong Park
19*54fd6939SJiyong Park #include <gpc.h>
20*54fd6939SJiyong Park #include <imx_sip_svc.h>
21*54fd6939SJiyong Park
imx_gpc_init(void)22*54fd6939SJiyong Park void imx_gpc_init(void)
23*54fd6939SJiyong Park {
24*54fd6939SJiyong Park unsigned int val;
25*54fd6939SJiyong Park int i;
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park /* mask all the wakeup irq by default */
28*54fd6939SJiyong Park for (i = 0; i < 4; i++) {
29*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
30*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
31*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
32*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
33*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
34*54fd6939SJiyong Park }
35*54fd6939SJiyong Park
36*54fd6939SJiyong Park val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
37*54fd6939SJiyong Park /* use GIC wake_request to wakeup C0~C3 from LPM */
38*54fd6939SJiyong Park val |= 0x30c00000;
39*54fd6939SJiyong Park /* clear the MASTER0 LPM handshake */
40*54fd6939SJiyong Park val &= ~(1 << 6);
41*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
42*54fd6939SJiyong Park
43*54fd6939SJiyong Park /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
44*54fd6939SJiyong Park mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
45*54fd6939SJiyong Park MASTER2_MAPPING));
46*54fd6939SJiyong Park
47*54fd6939SJiyong Park /* set all mix/PU in A53 domain */
48*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff);
49*54fd6939SJiyong Park
50*54fd6939SJiyong Park /*
51*54fd6939SJiyong Park * Set the CORE & SCU power up timing:
52*54fd6939SJiyong Park * SW = 0x1, SW2ISO = 0x1;
53*54fd6939SJiyong Park * the CPU CORE and SCU power up timming counter
54*54fd6939SJiyong Park * is drived by 32K OSC, each domain's power up
55*54fd6939SJiyong Park * latency is (SW + SW2ISO) / 32768
56*54fd6939SJiyong Park */
57*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81);
58*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81);
59*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81);
60*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81);
61*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81);
62*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
63*54fd6939SJiyong Park (0x59 << 10) | 0x5B | (0x2 << 20));
64*54fd6939SJiyong Park
65*54fd6939SJiyong Park /* set DUMMY PDN/PUP ACK by default for A53 domain */
66*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
67*54fd6939SJiyong Park A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
68*54fd6939SJiyong Park
69*54fd6939SJiyong Park /* clear DSM by default */
70*54fd6939SJiyong Park val = mmio_read_32(IMX_GPC_BASE + SLPCR);
71*54fd6939SJiyong Park val &= ~SLPCR_EN_DSM;
72*54fd6939SJiyong Park /* enable the fast wakeup wait mode */
73*54fd6939SJiyong Park val |= SLPCR_A53_FASTWUP_WAIT_MODE;
74*54fd6939SJiyong Park /* clear the RBC */
75*54fd6939SJiyong Park val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
76*54fd6939SJiyong Park /* set the STBY_COUNT to 0x5, (128 * 30)us */
77*54fd6939SJiyong Park val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
78*54fd6939SJiyong Park val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
79*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + SLPCR, val);
80*54fd6939SJiyong Park
81*54fd6939SJiyong Park /*
82*54fd6939SJiyong Park * USB PHY power up needs to make sure RESET bit in SRC is clear,
83*54fd6939SJiyong Park * otherwise, the PU power up bit in GPC will NOT self-cleared.
84*54fd6939SJiyong Park * only need to do it once.
85*54fd6939SJiyong Park */
86*54fd6939SJiyong Park mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
87*54fd6939SJiyong Park mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
88*54fd6939SJiyong Park
89*54fd6939SJiyong Park /* enable all the power domain by default */
90*54fd6939SJiyong Park mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf);
91*54fd6939SJiyong Park }
92