1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef IMX8M_GPC_H 8*54fd6939SJiyong Park #define IMX8M_GPC_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <gpc_reg.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* helper macro */ 13*54fd6939SJiyong Park #define A53_LPM_MASK U(0xF) 14*54fd6939SJiyong Park #define A53_LPM_WAIT U(0x5) 15*54fd6939SJiyong Park #define A53_LPM_STOP U(0xA) 16*54fd6939SJiyong Park #define LPM_MODE(local_state) ((local_state) == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP) 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park #define DSM_MODE_MASK BIT(31) 19*54fd6939SJiyong Park #define CORE_WKUP_FROM_GIC (IRQ_SRC_C0 | IRQ_SRC_C1 | IRQ_SRC_C2 | IRQ_SRC_C3) 20*54fd6939SJiyong Park #define A53_CORE_WUP_SRC(core_id) (1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2)) 21*54fd6939SJiyong Park #define COREx_PGC_PCR(core_id) (0x800 + (core_id) * 0x40) 22*54fd6939SJiyong Park #define COREx_WFI_PDN(core_id) (1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16)) 23*54fd6939SJiyong Park #define COREx_IRQ_WUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 8)) : (1 << ((core_id) * 2 + 20))) 24*54fd6939SJiyong Park #define COREx_LPM_PUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 + 21))) 25*54fd6939SJiyong Park #define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4))) 26*54fd6939SJiyong Park #define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2)) 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park #define IMR_MASK_ALL 0xffffffff 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park #define IMX_PD_DOMAIN(name, on) \ 31*54fd6939SJiyong Park { \ 32*54fd6939SJiyong Park .pwr_req = name##_PWR_REQ, \ 33*54fd6939SJiyong Park .pgc_offset = name##_PGC, \ 34*54fd6939SJiyong Park .need_sync = false, \ 35*54fd6939SJiyong Park .always_on = (on), \ 36*54fd6939SJiyong Park } 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park #define IMX_MIX_DOMAIN(name, on) \ 39*54fd6939SJiyong Park { \ 40*54fd6939SJiyong Park .pwr_req = name##_PWR_REQ, \ 41*54fd6939SJiyong Park .pgc_offset = name##_PGC, \ 42*54fd6939SJiyong Park .adb400_sync = name##_ADB400_SYNC, \ 43*54fd6939SJiyong Park .adb400_ack = name##_ADB400_ACK, \ 44*54fd6939SJiyong Park .need_sync = true, \ 45*54fd6939SJiyong Park .always_on = (on), \ 46*54fd6939SJiyong Park } 47*54fd6939SJiyong Park 48*54fd6939SJiyong Park struct imx_pwr_domain { 49*54fd6939SJiyong Park uint32_t pwr_req; 50*54fd6939SJiyong Park uint32_t adb400_sync; 51*54fd6939SJiyong Park uint32_t adb400_ack; 52*54fd6939SJiyong Park uint32_t pgc_offset; 53*54fd6939SJiyong Park bool need_sync; 54*54fd6939SJiyong Park bool always_on; 55*54fd6939SJiyong Park }; 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park DECLARE_BAKERY_LOCK(gpc_lock); 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park /* function declare */ 60*54fd6939SJiyong Park void imx_gpc_init(void); 61*54fd6939SJiyong Park void imx_set_cpu_secure_entry(unsigned int core_index, uintptr_t sec_entrypoint); 62*54fd6939SJiyong Park void imx_set_cpu_pwr_off(unsigned int core_index); 63*54fd6939SJiyong Park void imx_set_cpu_pwr_on(unsigned int core_index); 64*54fd6939SJiyong Park void imx_set_cpu_lpm(unsigned int core_index, bool pdn); 65*54fd6939SJiyong Park void imx_set_cluster_standby(bool retention); 66*54fd6939SJiyong Park void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state); 67*54fd6939SJiyong Park void imx_noc_slot_config(bool pdn); 68*54fd6939SJiyong Park void imx_set_sys_wakeup(unsigned int last_core, bool pdn); 69*54fd6939SJiyong Park void imx_set_sys_lpm(unsigned last_core, bool retention); 70*54fd6939SJiyong Park void imx_set_rbc_count(void); 71*54fd6939SJiyong Park void imx_clear_rbc_count(void); 72*54fd6939SJiyong Park 73*54fd6939SJiyong Park #endif /*IMX8M_GPC_H */ 74