1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <endian.h>
8*54fd6939SJiyong Park
9*54fd6939SJiyong Park #include <platform_def.h>
10*54fd6939SJiyong Park
11*54fd6939SJiyong Park #include <common/debug.h>
12*54fd6939SJiyong Park #include <lib/mmio.h>
13*54fd6939SJiyong Park
14*54fd6939SJiyong Park #include "soc_tzasc.h"
15*54fd6939SJiyong Park
tzc380_set_region(unsigned int tzasc_base,unsigned int region_id,unsigned int enabled,unsigned int low_addr,unsigned int high_addr,unsigned int size,unsigned int security,unsigned int subreg_disable_mask)16*54fd6939SJiyong Park int tzc380_set_region(unsigned int tzasc_base, unsigned int region_id,
17*54fd6939SJiyong Park unsigned int enabled, unsigned int low_addr,
18*54fd6939SJiyong Park unsigned int high_addr, unsigned int size,
19*54fd6939SJiyong Park unsigned int security, unsigned int subreg_disable_mask)
20*54fd6939SJiyong Park {
21*54fd6939SJiyong Park unsigned int reg;
22*54fd6939SJiyong Park unsigned int reg_base;
23*54fd6939SJiyong Park unsigned int attr_value;
24*54fd6939SJiyong Park
25*54fd6939SJiyong Park reg_base = (tzasc_base + TZASC_REGIONS_REG + (region_id << 4));
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park if (region_id == 0) {
28*54fd6939SJiyong Park reg = (reg_base + TZASC_REGION_ATTR_OFFSET);
29*54fd6939SJiyong Park mmio_write_32((uintptr_t)reg, ((security & 0xF) << 28));
30*54fd6939SJiyong Park } else {
31*54fd6939SJiyong Park reg = reg_base + TZASC_REGION_LOWADDR_OFFSET;
32*54fd6939SJiyong Park mmio_write_32((uintptr_t)reg,
33*54fd6939SJiyong Park (low_addr & TZASC_REGION_LOWADDR_MASK));
34*54fd6939SJiyong Park
35*54fd6939SJiyong Park reg = reg_base + TZASC_REGION_HIGHADDR_OFFSET;
36*54fd6939SJiyong Park mmio_write_32((uintptr_t)reg, high_addr);
37*54fd6939SJiyong Park
38*54fd6939SJiyong Park reg = reg_base + TZASC_REGION_ATTR_OFFSET;
39*54fd6939SJiyong Park attr_value = ((security & 0xF) << 28) |
40*54fd6939SJiyong Park ((subreg_disable_mask & 0xFF) << 8) |
41*54fd6939SJiyong Park ((size & 0x3F) << 1) | (enabled & 0x1);
42*54fd6939SJiyong Park mmio_write_32((uintptr_t)reg, attr_value);
43*54fd6939SJiyong Park
44*54fd6939SJiyong Park }
45*54fd6939SJiyong Park return 0;
46*54fd6939SJiyong Park }
47*54fd6939SJiyong Park
tzc380_setup(void)48*54fd6939SJiyong Park int tzc380_setup(void)
49*54fd6939SJiyong Park {
50*54fd6939SJiyong Park int reg_id = 0;
51*54fd6939SJiyong Park
52*54fd6939SJiyong Park INFO("Configuring TZASC-380\n");
53*54fd6939SJiyong Park
54*54fd6939SJiyong Park /*
55*54fd6939SJiyong Park * Configure CCI control override register to terminate all barrier
56*54fd6939SJiyong Park * transactions
57*54fd6939SJiyong Park */
58*54fd6939SJiyong Park mmio_write_32(PLAT_LS1043_CCI_BASE, CCI_TERMINATE_BARRIER_TX);
59*54fd6939SJiyong Park
60*54fd6939SJiyong Park /* Configure CSU secure access register to disable TZASC bypass mux */
61*54fd6939SJiyong Park mmio_write_32((uintptr_t)(CONFIG_SYS_FSL_CSU_ADDR +
62*54fd6939SJiyong Park CSU_SEC_ACCESS_REG_OFFSET),
63*54fd6939SJiyong Park bswap32(TZASC_BYPASS_MUX_DISABLE));
64*54fd6939SJiyong Park
65*54fd6939SJiyong Park for (reg_id = 0; reg_id < MAX_NUM_TZC_REGION; reg_id++) {
66*54fd6939SJiyong Park tzc380_set_region(CONFIG_SYS_FSL_TZASC_ADDR,
67*54fd6939SJiyong Park reg_id,
68*54fd6939SJiyong Park tzc380_reg_list[reg_id].enabled,
69*54fd6939SJiyong Park tzc380_reg_list[reg_id].low_addr,
70*54fd6939SJiyong Park tzc380_reg_list[reg_id].high_addr,
71*54fd6939SJiyong Park tzc380_reg_list[reg_id].size,
72*54fd6939SJiyong Park tzc380_reg_list[reg_id].secure,
73*54fd6939SJiyong Park tzc380_reg_list[reg_id].sub_mask);
74*54fd6939SJiyong Park }
75*54fd6939SJiyong Park
76*54fd6939SJiyong Park return 0;
77*54fd6939SJiyong Park }
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