1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef QEMU_PRIVATE_H 8*54fd6939SJiyong Park #define QEMU_PRIVATE_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <stdint.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park void qemu_configure_mmu_svc_mon(unsigned long total_base, 13*54fd6939SJiyong Park unsigned long total_size, 14*54fd6939SJiyong Park unsigned long code_start, unsigned long code_limit, 15*54fd6939SJiyong Park unsigned long ro_start, unsigned long ro_limit, 16*54fd6939SJiyong Park unsigned long coh_start, unsigned long coh_limit); 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size, 19*54fd6939SJiyong Park unsigned long code_start, unsigned long code_limit, 20*54fd6939SJiyong Park unsigned long ro_start, unsigned long ro_limit, 21*54fd6939SJiyong Park unsigned long coh_start, unsigned long coh_limit); 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size, 24*54fd6939SJiyong Park unsigned long code_start, unsigned long code_limit, 25*54fd6939SJiyong Park unsigned long ro_start, unsigned long ro_limit, 26*54fd6939SJiyong Park unsigned long coh_start, unsigned long coh_limit); 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park void plat_qemu_io_setup(void); 29*54fd6939SJiyong Park unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park void qemu_console_init(void); 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park void plat_qemu_gic_init(void); 34*54fd6939SJiyong Park void qemu_pwr_gic_on_finish(void); 35*54fd6939SJiyong Park void qemu_pwr_gic_off(void); 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park #endif /* QEMU_PRIVATE_H */ 38