1*67e74705SXin Li // REQUIRES: arm-registered-target
2*67e74705SXin Li // RUN: %clang_cc1 -triple thumbv7-apple-darwin \
3*67e74705SXin Li // RUN: -target-abi apcs-gnu \
4*67e74705SXin Li // RUN: -target-cpu cortex-a8 \
5*67e74705SXin Li // RUN: -mfloat-abi soft \
6*67e74705SXin Li // RUN: -target-feature +soft-float-abi \
7*67e74705SXin Li // RUN: -ffreestanding \
8*67e74705SXin Li // RUN: -emit-llvm -w -o - %s | FileCheck %s
9*67e74705SXin Li
10*67e74705SXin Li #include <arm_neon.h>
11*67e74705SXin Li
12*67e74705SXin Li // Radar 11998303: Avoid using i64 types for vld1q_lane and vst1q_lane Neon
13*67e74705SXin Li // intrinsics with <2 x i64> vectors to avoid poor code for i64 in the backend.
t1(uint64_t * src,uint8_t * dst)14*67e74705SXin Li void t1(uint64_t *src, uint8_t *dst) {
15*67e74705SXin Li // CHECK: @t1
16*67e74705SXin Li uint64x2_t q = vld1q_u64(src);
17*67e74705SXin Li // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8
18*67e74705SXin Li vst1q_lane_u64(dst, q, 1);
19*67e74705SXin Li // CHECK: bitcast <16 x i8> %{{.*}} to <2 x i64>
20*67e74705SXin Li // CHECK: shufflevector <2 x i64>
21*67e74705SXin Li // CHECK: call void @llvm.arm.neon.vst1.p0i8.v1i64
22*67e74705SXin Li }
23*67e74705SXin Li
t2(uint64_t * src1,uint8_t * src2,uint64x2_t * dst)24*67e74705SXin Li void t2(uint64_t *src1, uint8_t *src2, uint64x2_t *dst) {
25*67e74705SXin Li // CHECK: @t2
26*67e74705SXin Li uint64x2_t q = vld1q_u64(src1);
27*67e74705SXin Li // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8
28*67e74705SXin Li q = vld1q_lane_u64(src2, q, 0);
29*67e74705SXin Li // CHECK: shufflevector <2 x i64>
30*67e74705SXin Li // CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8
31*67e74705SXin Li // CHECK: shufflevector <1 x i64>
32*67e74705SXin Li *dst = q;
33*67e74705SXin Li // CHECK: store <2 x i64>
34*67e74705SXin Li }
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