1*67e74705SXin Li // REQUIRES: arm-registered-target
2*67e74705SXin Li // RUN: %clang_cc1 -triple thumbv7-apple-darwin \
3*67e74705SXin Li // RUN: -target-abi apcs-gnu \
4*67e74705SXin Li // RUN: -target-cpu cortex-a8 \
5*67e74705SXin Li // RUN: -mfloat-abi soft \
6*67e74705SXin Li // RUN: -target-feature +soft-float-abi \
7*67e74705SXin Li // RUN: -ffreestanding \
8*67e74705SXin Li // RUN: -emit-llvm -w -o - %s | FileCheck %s
9*67e74705SXin Li
10*67e74705SXin Li #include <arm_neon.h>
11*67e74705SXin Li
12*67e74705SXin Li // Radar 9311427: Check that alignment specifier is used in Neon load/store
13*67e74705SXin Li // intrinsics.
14*67e74705SXin Li typedef float AlignedAddr __attribute__ ((aligned (16)));
t1(AlignedAddr * addr1,AlignedAddr * addr2)15*67e74705SXin Li void t1(AlignedAddr *addr1, AlignedAddr *addr2) {
16*67e74705SXin Li // CHECK: @t1
17*67e74705SXin Li // CHECK: call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %{{.*}}, i32 16)
18*67e74705SXin Li float32x4_t a = vld1q_f32(addr1);
19*67e74705SXin Li // CHECK: call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %{{.*}}, <4 x float> %{{.*}}, i32 16)
20*67e74705SXin Li vst1q_f32(addr2, a);
21*67e74705SXin Li }
22*67e74705SXin Li
23*67e74705SXin Li // Radar 10538555: Make sure unaligned load/stores do not gain alignment.
t2(char * addr)24*67e74705SXin Li void t2(char *addr) {
25*67e74705SXin Li // CHECK: @t2
26*67e74705SXin Li // CHECK: load i32, i32* %{{.*}}, align 1
27*67e74705SXin Li int32x2_t vec = vld1_dup_s32(addr);
28*67e74705SXin Li // CHECK: store i32 %{{.*}}, i32* {{.*}}, align 1
29*67e74705SXin Li vst1_lane_s32(addr, vec, 1);
30*67e74705SXin Li }
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