1*67e74705SXin Li // REQUIRES: mips-registered-target
2*67e74705SXin Li // RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm -o - %s | FileCheck %s
3*67e74705SXin Li
4*67e74705SXin Li int data;
5*67e74705SXin Li
m()6*67e74705SXin Li void m () {
7*67e74705SXin Li asm("lw $1, %0" :: "m"(data));
8*67e74705SXin Li // CHECK: call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* @data)
9*67e74705SXin Li }
10*67e74705SXin Li
ZC()11*67e74705SXin Li void ZC () {
12*67e74705SXin Li asm("ll $1, %0" :: "ZC"(data));
13*67e74705SXin Li // CHECK: call void asm sideeffect "ll $$1, $0", "*^ZC,~{$1}"(i32* @data)
14*67e74705SXin Li }
15*67e74705SXin Li
R()16*67e74705SXin Li void R () {
17*67e74705SXin Li asm("lw $1, %0" :: "R"(data));
18*67e74705SXin Li // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data)
19*67e74705SXin Li }
20*67e74705SXin Li
additionalClobberedRegisters()21*67e74705SXin Li int additionalClobberedRegisters () {
22*67e74705SXin Li int temp0;
23*67e74705SXin Li asm volatile(
24*67e74705SXin Li "mfhi %[temp0], $ac1 \n\t"
25*67e74705SXin Li : [temp0]"=&r"(temp0)
26*67e74705SXin Li :
27*67e74705SXin Li : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo"
28*67e74705SXin Li );
29*67e74705SXin Li return 0;
30*67e74705SXin Li // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}"
31*67e74705SXin Li }
32