1*eca53ba6SRoland Levillain // Copyright 2017 Google LLC 2*eca53ba6SRoland Levillain // 3*eca53ba6SRoland Levillain // Licensed under the Apache License, Version 2.0 (the "License"); 4*eca53ba6SRoland Levillain // you may not use this file except in compliance with the License. 5*eca53ba6SRoland Levillain // You may obtain a copy of the License at 6*eca53ba6SRoland Levillain // 7*eca53ba6SRoland Levillain // http://www.apache.org/licenses/LICENSE-2.0 8*eca53ba6SRoland Levillain // 9*eca53ba6SRoland Levillain // Unless required by applicable law or agreed to in writing, software 10*eca53ba6SRoland Levillain // distributed under the License is distributed on an "AS IS" BASIS, 11*eca53ba6SRoland Levillain // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12*eca53ba6SRoland Levillain // See the License for the specific language governing permissions and 13*eca53ba6SRoland Levillain // limitations under the License. 14*eca53ba6SRoland Levillain 15*eca53ba6SRoland Levillain #ifndef CPU_FEATURES_INCLUDE_CPUINFO_MIPS_H_ 16*eca53ba6SRoland Levillain #define CPU_FEATURES_INCLUDE_CPUINFO_MIPS_H_ 17*eca53ba6SRoland Levillain 18*eca53ba6SRoland Levillain #include "cpu_features_cache_info.h" 19*eca53ba6SRoland Levillain #include "cpu_features_macros.h" 20*eca53ba6SRoland Levillain 21*eca53ba6SRoland Levillain CPU_FEATURES_START_CPP_NAMESPACE 22*eca53ba6SRoland Levillain 23*eca53ba6SRoland Levillain typedef struct { 24*eca53ba6SRoland Levillain int msa : 1; // MIPS SIMD Architecture 25*eca53ba6SRoland Levillain // https://www.mips.com/products/architectures/ase/simd/ 26*eca53ba6SRoland Levillain int eva : 1; // Enhanced Virtual Addressing 27*eca53ba6SRoland Levillain // https://www.mips.com/products/architectures/mips64/ 28*eca53ba6SRoland Levillain int r6 : 1; // True if is release 6 of the processor. 29*eca53ba6SRoland Levillain int mips16 : 1; // Compressed instructions 30*eca53ba6SRoland Levillain int mdmx : 1; // MIPS Digital Media Extension 31*eca53ba6SRoland Levillain int mips3d : 1; // 3D graphics acceleration 32*eca53ba6SRoland Levillain // MIPS(r) Architecture for Programmers, Volume IV-c 33*eca53ba6SRoland Levillain int smart : 1; // Smart-card cryptography 34*eca53ba6SRoland Levillain // MIPS(r) Architecture for Programmers, Volume IV-d 35*eca53ba6SRoland Levillain int dsp : 1; // Digital Signal Processing 36*eca53ba6SRoland Levillain // MIPS(r) Architecture for Programmers, Volume IV-e 37*eca53ba6SRoland Levillain // https://www.mips.com/products/architectures/ase/dsp/ 38*eca53ba6SRoland Levillain 39*eca53ba6SRoland Levillain // Make sure to update MipsFeaturesEnum below if you add a field here. 40*eca53ba6SRoland Levillain } MipsFeatures; 41*eca53ba6SRoland Levillain 42*eca53ba6SRoland Levillain typedef struct { 43*eca53ba6SRoland Levillain MipsFeatures features; 44*eca53ba6SRoland Levillain } MipsInfo; 45*eca53ba6SRoland Levillain 46*eca53ba6SRoland Levillain MipsInfo GetMipsInfo(void); 47*eca53ba6SRoland Levillain 48*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 49*eca53ba6SRoland Levillain // Introspection functions 50*eca53ba6SRoland Levillain 51*eca53ba6SRoland Levillain typedef enum { 52*eca53ba6SRoland Levillain MIPS_MSA, 53*eca53ba6SRoland Levillain MIPS_EVA, 54*eca53ba6SRoland Levillain MIPS_R6, 55*eca53ba6SRoland Levillain MIPS_MIPS16, 56*eca53ba6SRoland Levillain MIPS_MDMX, 57*eca53ba6SRoland Levillain MIPS_MIPS3D, 58*eca53ba6SRoland Levillain MIPS_SMART, 59*eca53ba6SRoland Levillain MIPS_DSP, 60*eca53ba6SRoland Levillain MIPS_LAST_, 61*eca53ba6SRoland Levillain } MipsFeaturesEnum; 62*eca53ba6SRoland Levillain 63*eca53ba6SRoland Levillain int GetMipsFeaturesEnumValue(const MipsFeatures* features, 64*eca53ba6SRoland Levillain MipsFeaturesEnum value); 65*eca53ba6SRoland Levillain 66*eca53ba6SRoland Levillain const char* GetMipsFeaturesEnumName(MipsFeaturesEnum); 67*eca53ba6SRoland Levillain 68*eca53ba6SRoland Levillain CPU_FEATURES_END_CPP_NAMESPACE 69*eca53ba6SRoland Levillain 70*eca53ba6SRoland Levillain #if !defined(CPU_FEATURES_ARCH_MIPS) 71*eca53ba6SRoland Levillain #error "Including cpuinfo_mips.h from a non-mips target." 72*eca53ba6SRoland Levillain #endif 73*eca53ba6SRoland Levillain 74*eca53ba6SRoland Levillain #endif // CPU_FEATURES_INCLUDE_CPUINFO_MIPS_H_ 75