1*c83a76b0SSuyog Pawar /****************************************************************************** 2*c83a76b0SSuyog Pawar * 3*c83a76b0SSuyog Pawar * Copyright (C) 2018 The Android Open Source Project 4*c83a76b0SSuyog Pawar * 5*c83a76b0SSuyog Pawar * Licensed under the Apache License, Version 2.0 (the "License"); 6*c83a76b0SSuyog Pawar * you may not use this file except in compliance with the License. 7*c83a76b0SSuyog Pawar * You may obtain a copy of the License at: 8*c83a76b0SSuyog Pawar * 9*c83a76b0SSuyog Pawar * http://www.apache.org/licenses/LICENSE-2.0 10*c83a76b0SSuyog Pawar * 11*c83a76b0SSuyog Pawar * Unless required by applicable law or agreed to in writing, software 12*c83a76b0SSuyog Pawar * distributed under the License is distributed on an "AS IS" BASIS, 13*c83a76b0SSuyog Pawar * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14*c83a76b0SSuyog Pawar * See the License for the specific language governing permissions and 15*c83a76b0SSuyog Pawar * limitations under the License. 16*c83a76b0SSuyog Pawar * 17*c83a76b0SSuyog Pawar ***************************************************************************** 18*c83a76b0SSuyog Pawar * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19*c83a76b0SSuyog Pawar */ 20*c83a76b0SSuyog Pawar /*! 21*c83a76b0SSuyog Pawar ****************************************************************************** 22*c83a76b0SSuyog Pawar * \file ihevce_dep_mngr_interface.h 23*c83a76b0SSuyog Pawar * 24*c83a76b0SSuyog Pawar * \brief 25*c83a76b0SSuyog Pawar * This file contains infertace prototypes of Sync manager functions 26*c83a76b0SSuyog Pawar * 27*c83a76b0SSuyog Pawar * \date 28*c83a76b0SSuyog Pawar * 13/12/2013 29*c83a76b0SSuyog Pawar * 30*c83a76b0SSuyog Pawar * \author 31*c83a76b0SSuyog Pawar * Ittiam 32*c83a76b0SSuyog Pawar * 33*c83a76b0SSuyog Pawar ****************************************************************************** 34*c83a76b0SSuyog Pawar */ 35*c83a76b0SSuyog Pawar 36*c83a76b0SSuyog Pawar #ifndef _IHEVCE_DEPENDENCY_MANAGER_INTERFACE_H_ 37*c83a76b0SSuyog Pawar #define _IHEVCE_DEPENDENCY_MANAGER_INTERFACE_H_ 38*c83a76b0SSuyog Pawar 39*c83a76b0SSuyog Pawar /*****************************************************************************/ 40*c83a76b0SSuyog Pawar /* Constant Macros */ 41*c83a76b0SSuyog Pawar /*****************************************************************************/ 42*c83a76b0SSuyog Pawar 43*c83a76b0SSuyog Pawar /*****************************************************************************/ 44*c83a76b0SSuyog Pawar /* Function Macros */ 45*c83a76b0SSuyog Pawar /*****************************************************************************/ 46*c83a76b0SSuyog Pawar 47*c83a76b0SSuyog Pawar /*****************************************************************************/ 48*c83a76b0SSuyog Pawar /* Typedefs */ 49*c83a76b0SSuyog Pawar /*****************************************************************************/ 50*c83a76b0SSuyog Pawar 51*c83a76b0SSuyog Pawar /*****************************************************************************/ 52*c83a76b0SSuyog Pawar /* Enums */ 53*c83a76b0SSuyog Pawar /*****************************************************************************/ 54*c83a76b0SSuyog Pawar 55*c83a76b0SSuyog Pawar typedef enum 56*c83a76b0SSuyog Pawar { 57*c83a76b0SSuyog Pawar DEP_MNGR_FRM_FRM_SYNC = 0, /*!< To be used for multi threads Frame- 58*c83a76b0SSuyog Pawar Frame level sync, where threads entering 59*c83a76b0SSuyog Pawar a particular frame processing stage at 60*c83a76b0SSuyog Pawar a particular index waits for all the threads 61*c83a76b0SSuyog Pawar to complete the that stage at the same index 62*c83a76b0SSuyog Pawar in the previous iteration 63*c83a76b0SSuyog Pawar Ex: Wait for Encloop at Index i frame 64*c83a76b0SSuyog Pawar to complete before starting encloop of 65*c83a76b0SSuyog Pawar MAX_NUM_ENCLOOP + i frame at Index i 66*c83a76b0SSuyog Pawar (FRAME LEVEl SYNCS)*/ 67*c83a76b0SSuyog Pawar 68*c83a76b0SSuyog Pawar DEP_MNGR_ROW_FRM_SYNC, /*!< To be used for multi threads Row- 69*c83a76b0SSuyog Pawar Frame level sync, where multiple threads 70*c83a76b0SSuyog Pawar entering a particular frame processing stage at 71*c83a76b0SSuyog Pawar a particular index waits for corresponding 72*c83a76b0SSuyog Pawar row to be completely processed in the 73*c83a76b0SSuyog Pawar dependent stage 74*c83a76b0SSuyog Pawar Ex: Multiple threads Wait in ME at a 75*c83a76b0SSuyog Pawar particular row X (of Frame I) 76*c83a76b0SSuyog Pawar until encloop of row X in Frame I 77*c83a76b0SSuyog Pawar is completed 78*c83a76b0SSuyog Pawar (REVERSE ME DEPENDENCY SYNC)*/ 79*c83a76b0SSuyog Pawar 80*c83a76b0SSuyog Pawar DEP_MNGR_ROW_ROW_SYNC, /*!< To be used for multi threads Row- 81*c83a76b0SSuyog Pawar Row level sync, where a thread 82*c83a76b0SSuyog Pawar entering a particular frame processing stage at 83*c83a76b0SSuyog Pawar a particular index waits for corresponding 84*c83a76b0SSuyog Pawar row to be processed til dependent position 85*c83a76b0SSuyog Pawar in the dependent stage 86*c83a76b0SSuyog Pawar Ex: (ENC LOOP to ME FORWARD Sync) 87*c83a76b0SSuyog Pawar ( TOP RIGHT SYNC) */ 88*c83a76b0SSuyog Pawar 89*c83a76b0SSuyog Pawar DEP_MNGR_MAP_SYNC 90*c83a76b0SSuyog Pawar 91*c83a76b0SSuyog Pawar } DEP_MNGR_MODE_T; 92*c83a76b0SSuyog Pawar 93*c83a76b0SSuyog Pawar typedef enum 94*c83a76b0SSuyog Pawar { 95*c83a76b0SSuyog Pawar MAP_CTB_INIT = 0, 96*c83a76b0SSuyog Pawar MAP_CTB_RECON_DONE = 1, 97*c83a76b0SSuyog Pawar MAP_CTB_COMPLETE = 2, //after hpel plane creation 98*c83a76b0SSuyog Pawar 99*c83a76b0SSuyog Pawar } DEP_MNGR_MAP_CTB_STATUS_T; 100*c83a76b0SSuyog Pawar 101*c83a76b0SSuyog Pawar /*****************************************************************************/ 102*c83a76b0SSuyog Pawar /* Structure */ 103*c83a76b0SSuyog Pawar /*****************************************************************************/ 104*c83a76b0SSuyog Pawar 105*c83a76b0SSuyog Pawar /*****************************************************************************/ 106*c83a76b0SSuyog Pawar /* Extern Variable Declarations */ 107*c83a76b0SSuyog Pawar /*****************************************************************************/ 108*c83a76b0SSuyog Pawar 109*c83a76b0SSuyog Pawar /*****************************************************************************/ 110*c83a76b0SSuyog Pawar /* Extern Function Declarations */ 111*c83a76b0SSuyog Pawar /*****************************************************************************/ 112*c83a76b0SSuyog Pawar 113*c83a76b0SSuyog Pawar /* Create APIs */ 114*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_get_num_mem_recs(void); 115*c83a76b0SSuyog Pawar 116*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_get_mem_recs( 117*c83a76b0SSuyog Pawar iv_mem_rec_t *ps_mem_tab, 118*c83a76b0SSuyog Pawar WORD32 dep_mngr_mode, /* should be part of DEP_MNGR_MODE_T*/ 119*c83a76b0SSuyog Pawar WORD32 max_num_vert_units, 120*c83a76b0SSuyog Pawar WORD32 num_tile_cols, 121*c83a76b0SSuyog Pawar WORD32 num_threads, 122*c83a76b0SSuyog Pawar WORD32 i4_mem_space); 123*c83a76b0SSuyog Pawar 124*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_map_get_mem_recs( 125*c83a76b0SSuyog Pawar iv_mem_rec_t *ps_mem_tab, WORD32 num_units, WORD32 num_threads, WORD32 i4_mem_space); 126*c83a76b0SSuyog Pawar 127*c83a76b0SSuyog Pawar void *ihevce_dmgr_init( 128*c83a76b0SSuyog Pawar iv_mem_rec_t *ps_mem_tab, 129*c83a76b0SSuyog Pawar void *pv_osal_handle, 130*c83a76b0SSuyog Pawar WORD32 dep_mngr_mode, /* should be part of DEP_MNGR_MODE_T*/ 131*c83a76b0SSuyog Pawar WORD32 max_num_vert_units, 132*c83a76b0SSuyog Pawar WORD32 max_num_horz_units, 133*c83a76b0SSuyog Pawar WORD32 num_tile_cols, 134*c83a76b0SSuyog Pawar WORD32 num_threads, 135*c83a76b0SSuyog Pawar WORD32 sem_enable); 136*c83a76b0SSuyog Pawar 137*c83a76b0SSuyog Pawar void *ihevce_dmgr_map_init( 138*c83a76b0SSuyog Pawar iv_mem_rec_t *ps_mem_tab, 139*c83a76b0SSuyog Pawar WORD32 max_num_vert_units, 140*c83a76b0SSuyog Pawar WORD32 max_num_horz_units, 141*c83a76b0SSuyog Pawar WORD32 sem_enable, 142*c83a76b0SSuyog Pawar WORD32 num_threads, 143*c83a76b0SSuyog Pawar WORD32 ai4_tile_xtra_ctb[4]); 144*c83a76b0SSuyog Pawar 145*c83a76b0SSuyog Pawar void ihevce_dmgr_reg_sem_hdls( 146*c83a76b0SSuyog Pawar void *pv_dep_mngr_state, void **ppv_thread_sem_hdl, WORD32 num_threads); 147*c83a76b0SSuyog Pawar 148*c83a76b0SSuyog Pawar /* Row-Row sync Process APIs*/ 149*c83a76b0SSuyog Pawar void ihevce_dmgr_rst_row_row_sync(void *pv_dep_mngr_state); 150*c83a76b0SSuyog Pawar 151*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_chk_row_row_sync( 152*c83a76b0SSuyog Pawar void *pv_dep_mngr_state, 153*c83a76b0SSuyog Pawar WORD32 cur_offset, 154*c83a76b0SSuyog Pawar WORD32 dep_offset, 155*c83a76b0SSuyog Pawar WORD32 dep_row, 156*c83a76b0SSuyog Pawar WORD32 cur_tile_col, 157*c83a76b0SSuyog Pawar WORD32 thrd_id); 158*c83a76b0SSuyog Pawar 159*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_set_row_row_sync( 160*c83a76b0SSuyog Pawar void *pv_dep_mngr_state, WORD32 cur_offset, WORD32 cur_row, WORD32 cur_tile_col); 161*c83a76b0SSuyog Pawar 162*c83a76b0SSuyog Pawar /* Row-Frame sync Process APIs*/ 163*c83a76b0SSuyog Pawar void ihevce_dmgr_rst_row_frm_sync(void *pv_dep_mngr_state); 164*c83a76b0SSuyog Pawar 165*c83a76b0SSuyog Pawar /* Frame-Frame sync Process APIs*/ 166*c83a76b0SSuyog Pawar void ihevce_dmgr_set_done_frm_frm_sync(void *pv_dep_mngr_state); 167*c83a76b0SSuyog Pawar 168*c83a76b0SSuyog Pawar void ihevce_dmgr_set_prev_done_frm_frm_sync(void *pv_dep_mngr_state); 169*c83a76b0SSuyog Pawar 170*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_chk_frm_frm_sync(void *pv_dep_mngr_state, WORD32 thrd_id); 171*c83a76b0SSuyog Pawar 172*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_update_frm_frm_sync(void *pv_dep_mngr_state); 173*c83a76b0SSuyog Pawar 174*c83a76b0SSuyog Pawar /* Map sync Process APIs*/ 175*c83a76b0SSuyog Pawar void ihevce_dmgr_map_rst_sync(void *pv_dep_mngr_state); 176*c83a76b0SSuyog Pawar 177*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_map_chk_sync( 178*c83a76b0SSuyog Pawar void *pv_dep_mngr_state, 179*c83a76b0SSuyog Pawar WORD32 thrd_id, 180*c83a76b0SSuyog Pawar WORD32 offset_x, 181*c83a76b0SSuyog Pawar WORD32 offset_y, 182*c83a76b0SSuyog Pawar WORD32 i4_sr_ctb_x, 183*c83a76b0SSuyog Pawar WORD32 i4_sr_ctb_y); 184*c83a76b0SSuyog Pawar 185*c83a76b0SSuyog Pawar WORD32 ihevce_dmgr_map_set_sync( 186*c83a76b0SSuyog Pawar void *pv_dep_mngr_state, WORD32 offset_x, WORD32 offset_y, WORD32 e_map_value); 187*c83a76b0SSuyog Pawar 188*c83a76b0SSuyog Pawar /* Delete APIs */ 189*c83a76b0SSuyog Pawar void ihevce_dmgr_del(void *pv_dep_mngr_state); 190*c83a76b0SSuyog Pawar 191*c83a76b0SSuyog Pawar #endif /* _IHEVCE_DEPENDENCY_MANAGER_INTERFACE_H_ */ 192