1*9880d681SAndroid Build Coastguard Worker//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===// 2*9880d681SAndroid Build Coastguard Worker// 3*9880d681SAndroid Build Coastguard Worker// The LLVM Compiler Infrastructure 4*9880d681SAndroid Build Coastguard Worker// 5*9880d681SAndroid Build Coastguard Worker// This file is distributed under the University of Illinois Open Source 6*9880d681SAndroid Build Coastguard Worker// License. See LICENSE.TXT for details. 7*9880d681SAndroid Build Coastguard Worker// 8*9880d681SAndroid Build Coastguard Worker//===----------------------------------------------------------------------===// 9*9880d681SAndroid Build Coastguard Worker// 10*9880d681SAndroid Build Coastguard Worker// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction 11*9880d681SAndroid Build Coastguard Worker// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS 12*9880d681SAndroid Build Coastguard Worker// slot has been removed. 13*9880d681SAndroid Build Coastguard Worker// 14*9880d681SAndroid Build Coastguard Worker//===----------------------------------------------------------------------===// 15*9880d681SAndroid Build Coastguard Worker 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Workerdef ALU_X : FuncUnit; 18*9880d681SAndroid Build Coastguard Workerdef ALU_Y : FuncUnit; 19*9880d681SAndroid Build Coastguard Workerdef ALU_Z : FuncUnit; 20*9880d681SAndroid Build Coastguard Workerdef ALU_W : FuncUnit; 21*9880d681SAndroid Build Coastguard Workerdef TRANS : FuncUnit; 22*9880d681SAndroid Build Coastguard Worker 23*9880d681SAndroid Build Coastguard Workerdef AnyALU : InstrItinClass; 24*9880d681SAndroid Build Coastguard Workerdef VecALU : InstrItinClass; 25*9880d681SAndroid Build Coastguard Workerdef TransALU : InstrItinClass; 26*9880d681SAndroid Build Coastguard Workerdef XALU : InstrItinClass; 27*9880d681SAndroid Build Coastguard Worker 28*9880d681SAndroid Build Coastguard Workerdef R600_VLIW5_Itin : ProcessorItineraries < 29*9880d681SAndroid Build Coastguard Worker [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL], 30*9880d681SAndroid Build Coastguard Worker [], 31*9880d681SAndroid Build Coastguard Worker [ 32*9880d681SAndroid Build Coastguard Worker InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>, 33*9880d681SAndroid Build Coastguard Worker InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 34*9880d681SAndroid Build Coastguard Worker InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>, 35*9880d681SAndroid Build Coastguard Worker InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>, 36*9880d681SAndroid Build Coastguard Worker InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> 37*9880d681SAndroid Build Coastguard Worker ] 38*9880d681SAndroid Build Coastguard Worker>; 39*9880d681SAndroid Build Coastguard Worker 40*9880d681SAndroid Build Coastguard Workerdef R600_VLIW4_Itin : ProcessorItineraries < 41*9880d681SAndroid Build Coastguard Worker [ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL], 42*9880d681SAndroid Build Coastguard Worker [], 43*9880d681SAndroid Build Coastguard Worker [ 44*9880d681SAndroid Build Coastguard Worker InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 45*9880d681SAndroid Build Coastguard Worker InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 46*9880d681SAndroid Build Coastguard Worker InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>, 47*9880d681SAndroid Build Coastguard Worker InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> 48*9880d681SAndroid Build Coastguard Worker ] 49*9880d681SAndroid Build Coastguard Worker>; 50