xref: /aosp_15_r20/external/llvm/test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -march arm64 -mcpu=cyclone | FileCheck %s
2*9880d681SAndroid Build Coastguard Worker; <rdar://problem/11294426>
3*9880d681SAndroid Build Coastguard Worker
4*9880d681SAndroid Build Coastguard Worker@b = private unnamed_addr constant [3 x i32] [i32 1768775988, i32 1685481784, i32 1836253201], align 4
5*9880d681SAndroid Build Coastguard Worker
6*9880d681SAndroid Build Coastguard Worker; The important thing for this test is that we need an unaligned load of `l_b'
7*9880d681SAndroid Build Coastguard Worker; ("ldr w2, [x1, #8]" in this case).
8*9880d681SAndroid Build Coastguard Worker
9*9880d681SAndroid Build Coastguard Worker; CHECK:      adrp x[[PAGE:[0-9]+]], {{l_b@PAGE|.Lb}}
10*9880d681SAndroid Build Coastguard Worker; CHECK: add  x[[ADDR:[0-9]+]], x[[PAGE]], {{l_b@PAGEOFF|:lo12:.Lb}}
11*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: ldr  [[VAL:w[0-9]+]], [x[[ADDR]], #8]
12*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: str  [[VAL]], [x0, #8]
13*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: ldr  [[VAL2:x[0-9]+]], [x[[ADDR]]]
14*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: str  [[VAL2]], [x0]
15*9880d681SAndroid Build Coastguard Worker
16*9880d681SAndroid Build Coastguard Workerdefine void @foo(i8* %a) {
17*9880d681SAndroid Build Coastguard Worker  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast ([3 x i32]* @b to i8*), i64 12, i32 4, i1 false)
18*9880d681SAndroid Build Coastguard Worker  ret void
19*9880d681SAndroid Build Coastguard Worker}
20*9880d681SAndroid Build Coastguard Worker
21*9880d681SAndroid Build Coastguard Workerdeclare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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