1*cda5da8dSAndroid Build Coastguard Worker /* 2*cda5da8dSAndroid Build Coastguard Worker * This file is auto-generated. Modifications will be lost. 3*cda5da8dSAndroid Build Coastguard Worker * 4*cda5da8dSAndroid Build Coastguard Worker * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5*cda5da8dSAndroid Build Coastguard Worker * for more information. 6*cda5da8dSAndroid Build Coastguard Worker */ 7*cda5da8dSAndroid Build Coastguard Worker #ifndef _UAPI_LINUX_FPGA_DFL_H 8*cda5da8dSAndroid Build Coastguard Worker #define _UAPI_LINUX_FPGA_DFL_H 9*cda5da8dSAndroid Build Coastguard Worker #include <linux/types.h> 10*cda5da8dSAndroid Build Coastguard Worker #include <linux/ioctl.h> 11*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_API_VERSION 0 12*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_MAGIC 0xB6 13*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_BASE 0 14*cda5da8dSAndroid Build Coastguard Worker #define DFL_PORT_BASE 0x40 15*cda5da8dSAndroid Build Coastguard Worker #define DFL_FME_BASE 0x80 16*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) 17*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) 18*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) 19*cda5da8dSAndroid Build Coastguard Worker struct dfl_fpga_port_info { 20*cda5da8dSAndroid Build Coastguard Worker __u32 argsz; 21*cda5da8dSAndroid Build Coastguard Worker __u32 flags; 22*cda5da8dSAndroid Build Coastguard Worker __u32 num_regions; 23*cda5da8dSAndroid Build Coastguard Worker __u32 num_umsgs; 24*cda5da8dSAndroid Build Coastguard Worker }; 25*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1) 26*cda5da8dSAndroid Build Coastguard Worker struct dfl_fpga_port_region_info { 27*cda5da8dSAndroid Build Coastguard Worker __u32 argsz; 28*cda5da8dSAndroid Build Coastguard Worker __u32 flags; 29*cda5da8dSAndroid Build Coastguard Worker #define DFL_PORT_REGION_READ (1 << 0) 30*cda5da8dSAndroid Build Coastguard Worker #define DFL_PORT_REGION_WRITE (1 << 1) 31*cda5da8dSAndroid Build Coastguard Worker #define DFL_PORT_REGION_MMAP (1 << 2) 32*cda5da8dSAndroid Build Coastguard Worker __u32 index; 33*cda5da8dSAndroid Build Coastguard Worker #define DFL_PORT_REGION_INDEX_AFU 0 34*cda5da8dSAndroid Build Coastguard Worker #define DFL_PORT_REGION_INDEX_STP 1 35*cda5da8dSAndroid Build Coastguard Worker __u32 padding; 36*cda5da8dSAndroid Build Coastguard Worker __u64 size; 37*cda5da8dSAndroid Build Coastguard Worker __u64 offset; 38*cda5da8dSAndroid Build Coastguard Worker }; 39*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) 40*cda5da8dSAndroid Build Coastguard Worker struct dfl_fpga_port_dma_map { 41*cda5da8dSAndroid Build Coastguard Worker __u32 argsz; 42*cda5da8dSAndroid Build Coastguard Worker __u32 flags; 43*cda5da8dSAndroid Build Coastguard Worker __u64 user_addr; 44*cda5da8dSAndroid Build Coastguard Worker __u64 length; 45*cda5da8dSAndroid Build Coastguard Worker __u64 iova; 46*cda5da8dSAndroid Build Coastguard Worker }; 47*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3) 48*cda5da8dSAndroid Build Coastguard Worker struct dfl_fpga_port_dma_unmap { 49*cda5da8dSAndroid Build Coastguard Worker __u32 argsz; 50*cda5da8dSAndroid Build Coastguard Worker __u32 flags; 51*cda5da8dSAndroid Build Coastguard Worker __u64 iova; 52*cda5da8dSAndroid Build Coastguard Worker }; 53*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4) 54*cda5da8dSAndroid Build Coastguard Worker struct dfl_fpga_irq_set { 55*cda5da8dSAndroid Build Coastguard Worker __u32 start; 56*cda5da8dSAndroid Build Coastguard Worker __u32 count; 57*cda5da8dSAndroid Build Coastguard Worker __s32 evtfds[]; 58*cda5da8dSAndroid Build Coastguard Worker }; 59*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5, __u32) 60*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6, struct dfl_fpga_irq_set) 61*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_UINT_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7, __u32) 62*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_PORT_UINT_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8, struct dfl_fpga_irq_set) 63*cda5da8dSAndroid Build Coastguard Worker struct dfl_fpga_fme_port_pr { 64*cda5da8dSAndroid Build Coastguard Worker __u32 argsz; 65*cda5da8dSAndroid Build Coastguard Worker __u32 flags; 66*cda5da8dSAndroid Build Coastguard Worker __u32 port_id; 67*cda5da8dSAndroid Build Coastguard Worker __u32 buffer_size; 68*cda5da8dSAndroid Build Coastguard Worker __u64 buffer_address; 69*cda5da8dSAndroid Build Coastguard Worker }; 70*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) 71*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int) 72*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int) 73*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_FME_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3, __u32) 74*cda5da8dSAndroid Build Coastguard Worker #define DFL_FPGA_FME_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4, struct dfl_fpga_irq_set) 75*cda5da8dSAndroid Build Coastguard Worker #endif 76