AXI4IntrGenerator.scala (964c1fbcf46544f07d70f9b5daafa9313934e9f4) AXI4IntrGenerator.scala (3c02ee8f82edea481fa8336c7f54ffc17fafba91)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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16
17package device
18
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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16
17package device
18
19import chisel3._
20import chisel3.util._
21import chipsalliance.rocketchip.config.Parameters
22import freechips.rocketchip.diplomacy.AddressSet
23import utils._
24import utility._
24
25// we support 256 interrupt bits by default
26class IntrGenIO extends Bundle {
27 val intrVec = Output(UInt(64.W))
28}
29
30class AXI4IntrGenerator
31(

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26// we support 256 interrupt bits by default
27class IntrGenIO extends Bundle {
28 val intrVec = Output(UInt(64.W))
29}
30
31class AXI4IntrGenerator
32(

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