History log of /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala (Results 1 – 8 of 8)
Revision Date Author Comments
# ad7236cd 11-Dec-2024 Tang Haojin <[email protected]>

fix(AXI4IntrGenerator): extract wdata according to waddr (#4022)


# 8891a219 08-Oct-2023 Yinan Xu <[email protected]>

Bump rocket-chip (#2353)


# 3c02ee8f 25-Dec-2022 wakafa <[email protected]>

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun


# 964c1fbc 28-Apr-2022 Yinan Xu <[email protected]>

intrGen: delay interrupts for 1000 cycles

To test WFI, we delay the interrupts for more cycles.


# 151b6d60 02-Dec-2021 Yinan Xu <[email protected]>

device,intrGen: add randomly generated interrupts (#1287)


# f320e0f0 24-Jul-2021 Yinan Xu <[email protected]>

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.


# c6d43980 04-Jun-2021 Lemover <[email protected]>

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.


# b6a21a24 25-May-2021 Yinan Xu <[email protected]>

device: add AXI4IntrGenerator to generate external interrupts (#819)

This commit adds a new AXI4 device to generate external interrupts.
Previously none of the simulated external devices trigger in

device: add AXI4IntrGenerator to generate external interrupts (#819)

This commit adds a new AXI4 device to generate external interrupts.
Previously none of the simulated external devices trigger interrupts.
To test external interrupts, we add this device.

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