AXI4Memory.scala (04ac809e6df52b85378bdf2065d2e91e490dc351) | AXI4Memory.scala (3c02ee8f82edea481fa8336c7f54ffc17fafba91) |
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1/*************************************************************************************** 2 * Copyright (c) 2020-2022 Institute of Computing Technology, Chinese Academy of Sciences 3 * 4 * XiangShan is licensed under Mulan PSL v2. 5 * You can use this software according to the terms and conditions of the Mulan PSL v2. 6 * You may obtain a copy of Mulan PSL v2 at: 7 * http://license.coscl.org.cn/MulanPSL2 8 * --- 8 unchanged lines hidden (view full) --- 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.experimental.ExtModule 21import chisel3.util._ 22import freechips.rocketchip.amba.axi4.{AXI4MasterNode, AXI4Parameters, AXI4SlaveNode} 23import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp} 24import utils._ | 1/*************************************************************************************** 2 * Copyright (c) 2020-2022 Institute of Computing Technology, Chinese Academy of Sciences 3 * 4 * XiangShan is licensed under Mulan PSL v2. 5 * You can use this software according to the terms and conditions of the Mulan PSL v2. 6 * You may obtain a copy of Mulan PSL v2 at: 7 * http://license.coscl.org.cn/MulanPSL2 8 * --- 8 unchanged lines hidden (view full) --- 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.experimental.ExtModule 21import chisel3.util._ 22import freechips.rocketchip.amba.axi4.{AXI4MasterNode, AXI4Parameters, AXI4SlaveNode} 23import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp} 24import utils._ |
25import utility._ |
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25 26class MemoryRWHelper extends ExtModule with HasExtModuleInline { 27 val DataBits = 64 28 29 val clock = IO(Input(Clock())) 30 val reset = IO(Input(Reset())) 31 val ren = IO(Input(Bool())) 32 val rIdx = IO(Input(UInt(DataBits.W))) --- 349 unchanged lines hidden --- | 26 27class MemoryRWHelper extends ExtModule with HasExtModuleInline { 28 val DataBits = 64 29 30 val clock = IO(Input(Clock())) 31 val reset = IO(Input(Reset())) 32 val ren = IO(Input(Bool())) 33 val rIdx = IO(Input(UInt(DataBits.W))) --- 349 unchanged lines hidden --- |