fix(AXI4Memory): fix write request enqueue DRAMSim logic for AXI4Memory (#4611)

fix(AXI4Memory): remove `AWLEN == 0` Check (#4383)

fix(AXI4Memory): fix loss of `r` channel packet (#4176)

Co-authored-by: zhanglinjuan <[email protected]>

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

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axi4-memory: reduce DPI-C calls (#2859)

This commit avoids querying dramsim when there are
no memory access requests. This change reduces DPIC
overhead by 70%-80%.

AXI4Memory: use synchronous read mem (#2741)

This commit adds one more cycle latency when DRAMsim is
enabled due to the extra one-cycle read latency of SRAM. To
run faster on palladium, we need th

AXI4Memory: use synchronous read mem (#2741)

This commit adds one more cycle latency when DRAMsim is
enabled due to the extra one-cycle read latency of SRAM. To
run faster on palladium, we need this.

Co-authored-by: Yinan Xu <[email protected]>

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Bump difftest (#2391)

* use the abstract DifftestMem class
* move DifftestModule.finish to hardware

Bump rocket-chip (#2353)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

sim: fix typo in AXI4 memory slave model (#1805)

* axi4,mem: fix typo for pending_write_resp_id

* axi4,mem: fix has_write_resp condition

sim: add AXI4 memory slave model in Chisel (#1799)