TLPMA.scala (98c716025d86d6220b2762171d9383f72e72cfe7) TLPMA.scala (3c02ee8f82edea481fa8336c7f54ffc17fafba91)
1package device
2
3import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp, SimpleDevice}
4import chipsalliance.rocketchip.config.Parameters
5import chisel3._
6import chisel3.util._
7import xiangshan._
8import utils._
1package device
2
3import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp, SimpleDevice}
4import chipsalliance.rocketchip.config.Parameters
5import chisel3._
6import chisel3.util._
7import xiangshan._
8import utils._
9import utility._
9import freechips.rocketchip.regmapper.RegFieldGroup
10import freechips.rocketchip.tilelink.TLRegisterNode
11import xiangshan.backend.fu.{MMPMAMethod, PMAConst, PMPChecker, PMPReqBundle, PMPRespBundle}
12
13class TLPMAIO(implicit val p: Parameters) extends Bundle with PMAConst {
14 val req = Vec(mmpma.num, Flipped(Valid(new PMPReqBundle(mmpma.lgMaxSize))))
15 val resp = Vec(mmpma.num, new PMPRespBundle())
16}

--- 42 unchanged lines hidden --- 		10import freechips.rocketchip.regmapper.RegFieldGroup
11import freechips.rocketchip.tilelink.TLRegisterNode
12import xiangshan.backend.fu.{MMPMAMethod, PMAConst, PMPChecker, PMPReqBundle, PMPRespBundle}
13
14class TLPMAIO(implicit val p: Parameters) extends Bundle with PMAConst {
15 val req = Vec(mmpma.num, Flipped(Valid(new PMPReqBundle(mmpma.lgMaxSize))))
16 val resp = Vec(mmpma.num, new PMPRespBundle())
17}

--- 42 unchanged lines hidden ---